ECSS-E-ST-50-14C
31 July 2008
Space engineering
Spacecraft discrete interfaces
ECSS Secretariat
ESA-ESTEC
Requirements & Standards Division
Noordwijk, The Netherlands
ECSSEST5014C
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Foreword
This Standard is one of the series of ECSS Standards intended to be applied together for the
management, engineering and product assurance in space projects and applications. ECSS is a
cooperative effort of the European Space Agency, national space agencies and European industry
associationsforthepurposeofdevelopingand
maintainingcommonstandards.Requirementsinthis
Standardaredefinedintermsofwhatshallbeaccomplished,ratherthanintermsofhowtoorganize
and perform the necessary work. This allows existing organizational structures and methods to be
appliedwheretheyareeffective,andforthestructuresandmethodstoevolve
asnecessarywithout
rewritingthestandards.
This Standard has been preparedby theECSSEST5014C Working Group, reviewed bythe ECSS
ExecutiveSecretariatandapprovedbytheECSSTechnicalAuthority.
Disclaimer
ECSSdoesnotprovideanywarrantywhatsoever,whetherexpressed,implied,orstatutory,including,
butnotlimitedto,
anywarrantyofmerchantabilityorfitnessforaparticularpurposeoranywarranty
that the contents of the item are errorfree. In no respect shall ECSS incur any liability for any
damages,including,butnotlimitedto,direct,indirect,special,orconsequentialdamagesarisingout
of,resultingfrom,or
inanyway connectedto the use ofthisStandard,whether or notbased upon
warranty,businessagreement,tort,orotherwise;whetherornotinjurywassustainedbypersonsor
propertyorotherwise;andwhetherornotlosswassustainedfrom,oraroseoutof,theresults of,the
item,or
anyservicesthatmaybeprovidedbyECSS.
Publishedby: ESARequirementsandStandardsDivision
ESTEC, P.O. Box 299,
2200 AG Noordwijk
The Netherlands
Copyright: 2008 © by the European Space Agency for the members of ECSS
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Change log
ECSSE5014A
19December2007
Firstissue
ECSSE5014B Neverissued
ECSSEST5014C
31July2008
Secondissue
Editorialchanges.
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Table of contents
Change log.................................................................................................................3
1 Scope.......................................................................................................................8
2 Normative references.............................................................................................9
3 Terms, definitions and abbreviated terms..........................................................10
3.1 Terms from other standards .....................................................................................10
3.2 Terms specific to the present standard ....................................................................10
3.3 Abbreviated terms ....................................................................................................11
3.4 Conventions .............................................................................................................12
3.4.1 Bit numbering convention...........................................................................12
3.4.2 Timing diagram conventions.......................................................................12
3.4.3 Signal and signal event naming convention ...............................................13
3.4.4 Signal timing and measurement references...............................................14
4 General ..................................................................................................................15
4.1 Introduction...............................................................................................................15
4.2 Architectural concepts..............................................................................................15
4.2.1 Overview.....................................................................................................15
4.2.2 General failure tolerance ............................................................................16
4.2.3 Interface control during power cycling........................................................17
4.2.4 Cross-strapping ..........................................................................................18
4.2.5 Harness cross-strapping.............................................................................19
4.2.6 Cable capacitance......................................................................................22
5 Analogue signal interfaces..................................................................................23
5.1 Overview ..................................................................................................................23
5.2 Analogue signal monitor (ASM) interface.................................................................23
5.2.1 General.......................................................................................................23
5.2.2 Analogue signal monitor interface ..............................................................25
5.3 Temperature sensors monitor (TSM) interface.........................................................27
5.3.1 Overview.....................................................................................................27
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5.3.2 TSM acquisition layout ...............................................................................28
5.3.3 TSM acquisition resolution .........................................................................28
5.3.4 TSM wire configuration...............................................................................28
5.3.5 TSM electrical characteristics.....................................................................29
6 Bi-level discrete input interfaces ........................................................................37
6.1 Bi-level discrete monitor (BDM) interface.................................................................37
6.1.1 Overview.....................................................................................................37
6.1.2 Bi-level discrete monitor interface ..............................................................37
6.2 Bi-level switch monitor (BSM) interface....................................................................39
6.2.1 General principles.......................................................................................39
6.2.2 Bi-level switch monitor interface.................................................................40
7 Pulsed command interfaces................................................................................42
7.1 High power command (HPC) interfaces...................................................................42
7.1.1 General principles.......................................................................................42
7.1.2 High power command interface..................................................................42
7.1.3 Low voltage high power command (LV-HPC) electrical characteristics .....43
7.1.4 High voltage high power command (HV-HPC) electrical
characteristics.............................................................................................45
7.1.5 High current high power command (HC-HPC) electrical
characteristics.............................................................................................46
7.1.6 Wiring type..................................................................................................47
7.1.7 High power command interface arrangement ............................................47
7.2 Low power command (LPC) interface ......................................................................48
7.2.1 General.......................................................................................................48
7.2.2 Low power command interface...................................................................48
7.2.3 LPC electrical characteristics .....................................................................49
7.2.4 Wiring type..................................................................................................50
7.2.5 Interface arrangement ................................................................................50
8 Serial digital interfaces ........................................................................................51
8.1 Foreword ..................................................................................................................51
8.2 General principles of serial digital interfaces............................................................51
8.2.1 Overview.....................................................................................................51
8.2.2 General requirements.................................................................................52
8.3 16-bit input serial digital (ISD) interface ...................................................................53
8.3.1 16-bit input serial digital interface description.............................................53
8.3.2 Signals skew...............................................................................................53
8.3.3 ISD interface timing specification ...............................................................53
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8.3.4 16-bit input serial digital interface: signal description .................................56
8.4 16-bit output serial digital (OSD) interface description.............................................58
8.4.1 16-bit output serial digital interface description ..........................................58
8.4.2 Signals skew...............................................................................................58
8.4.3 OSD interface timing specification..............................................................59
8.4.4 16-bit output serial digital interface signal description................................60
8.5 16-bit bi-directional serial digital (BSD) interface description ...................................62
8.6 Serial digital interface electrical circuits description .................................................63
8.7 Balanced differential serial digital interface signals..................................................64
8.7.1 Balanced differential serial digital interface - GATE_WRITE circuits .........64
8.7.2 Balanced differential serial digital interface - DATA_CLK_OUT circuits.....64
8.7.3 Balanced differential serial digital interface - DATA_OUT circuits..............64
8.7.4 Balanced differential serial digital interface - DATA_IN circuits..................65
8.7.5 Balanced differential serial digital interface - GATE_READ circuits...........65
8.8 Serial digital interface circuit electrical characteristics..............................................65
8.8.1 Introduction.................................................................................................65
8.8.2 Provisions...................................................................................................65
Annex A (informative) Tailoring guidelines...........................................................69
Bibliography.............................................................................................................70
Figures
Figure 3-1: Bit numbering convention ....................................................................................12
Figure 3-2: Timing diagram conventions................................................................................13
Figure 3-3: Signal timing and measurement references ........................................................14
Figure 4-1: Architectural context of interfaces defined in this standard..................................16
Figure 4-2: General scheme of redundant unit’s cross-strapping ..........................................18
Figure 4-3: Example scheme for Single source – Dual receiver cross-strapping...................20
Figure 4-4: Example scheme for Dual source – Single receiver cross-strapping...................21
Figure 4-5: Cable capacitance definitions ..............................................................................22
Figure 5-1: Analogue signal monitor (single ended source) interface arrangement..............27
Figure 5-2: Analogue signal monitor (differential source) interface arrangement .................27
Figure 5-3: TSM1 reference model ........................................................................................30
Figure 5-4: Requirement for ΔR
th
/R
th
as a function of R
NORM
and R
th
. Δx = ±0,01 .................30
Figure 5-5: TSM1 interface arrangement ...............................................................................32
Figure 5-6: TSM2 interface arrangement ...............................................................................34
Figure 5-7: Example TSM1 and 4K3A354 thermistor.............................................................35
Figure 5-8: Example TSM1 and YSI44907 thermistor............................................................35
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Figure 5-9: Example TSM2 and PT1000 thermistor...............................................................36
Figure 6-1: BDM Interface configuration ................................................................................39
Figure 6-2: Switch status circuit interface arrangement .........................................................41
Figure 7-1: HPC interface arrangement .................................................................................47
Figure 7-2: LPC active signal output voltage vs. load current................................................49
Figure 7-3: LPC-P and LPC-S interface arrangement............................................................50
Figure 8-1: 16-bit input serial digital (ISD) interface signal arrangement ...............................53
Figure 8-2: 16-bit input serial digital (ISD) interface...............................................................54
Figure 8-3: 16-bit output serial digital (OSD) interface signal arrangement ...........................58
Figure 8-4: 16-bit output serial digital (OSD) interface...........................................................59
Figure 8-5: 16-bit bi-directional serial digital interface signal arrangement ............................63
Figure 8-6: Balanced differential circuits for serial digital interfaces ......................................64
Figure 8-7: Example of serial digital interface arrangement...................................................66
Figure 8-8: Threshold levels for ECSS-E-50-14 differential circuits.......................................68
Tables
Table 5-1: Analogue signal monitor source circuit characteristics .........................................25
Table 5-2 Analogue signal receiver circuit characteristics .....................................................26
Table 5-3: TSM1 source circuit characteristics ......................................................................30
Table 5-4: TSM1 receiver circuit characteristics ....................................................................31
Table 5-5: TSM2 source characteristics.................................................................................33
Table 5-6: TSM2 receiver characteristics...............................................................................33
Table 6-1: BDM source characteristics ..................................................................................38
Table 6-2: BDM receiver characteristics ................................................................................38
Table 6-3: Switch source characteristics................................................................................40
Table 6-4: Switch receiver characteristics..............................................................................41
Table 7-1: LV-HPC source characteristics .............................................................................44
Table 7-2: LV-HPC receiver characteristics ...........................................................................44
Table 7-3: HV-HPC source characteristics.............................................................................45
Table 7-4: HV-HPC receiver characteristics...........................................................................46
Table 7-5: HC-HPC source characteristics ............................................................................46
Table 7-6: HC-HPC receiver characteristics ..........................................................................47
Table 7-7: LPC source characteristics ...................................................................................49
Table 7-8: LPC receiver characteristics .................................................................................50
Table 8-1: 16-bit input serial digital (ISD) interface characteristics ........................................55
Table 8-2: t
b
values ................................................................................................................57
Table 8-3: 16-bit output serial digital (OSD) interface characteristics ....................................60
Table 8-4: Serial digital interface electrical characteristics.....................................................67
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1
Scope
Thisstandardspecifiesacommonsetofspacecraftonboardelectricalinterfaces
for sensor acquisition and actuator control. The interfaces specified in this
standard are the traditional pointtopoint interfaces that are commonly used
onmodernspacecraft.
Theinterfacesspecified in thisstandardinclude analogueand discrete digital
interfaces used for
status measurement and control, as well as pointtopoint
serial digital interfaces used for digital data acquisition and commanding of
devices.
Thisstandardspecifies:
interfacesignalidentification;
interfacesignalwaveforms;
signaltimingrequirements;
signalmodulation;
voltagelevels;
inputandoutputimpedance;
overvoltage
protectionrequirements;
bitorderingindigitaldatawords;
cablingrequirementswhereappropriate.
Thisstandarddoesnotcover:
connectorrequirements;
digitaldatawordsemantics;
messageorblockformatsandsemantics.
Connectorrequirementsarenotcoveredbecausethesearenormallymissionor
project specific. The goal of this
standard is to establish a single set of
definitionsfortheseinterfacesandtopromotegenericimplementationsthatcan
bereusedthroughoutdifferentmissions.
When referred, the present standard is applicable as a complement of the
already existing interface standards ANSI/TIA/EIA422B1994 and ITUT
RecommendationV.11(Previously
“CCITTRecommendation”)(03/93).
GuidancefortailoringofthepresentstandardcanbefoundinAnnexA.
ThisStandardmaybetailoredforthespecificcharacteristicsandconstraintsof
aspaceprojectinconformancewithECSSSST00.
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2
Normative references
The following normative documents contain provisions which, through
reference in this text, constitute provisions of this ECSS Standard. For dated
references, subsequent amendments to, or revisions of any of these
publications,donotapply.However,partiestoagreementsbasedonthisECSS
Standard are encouraged to investigate the possibility of applying
the most
recent editions of the normative documents indicated below. For undated
referencesthelatesteditionofthepublicationreferredtoapplies.
ECSSSST0001 ECSSsystem‐Glossaryofterms
ANSI/TIA/EIA422B1994 Electricalcharacteristicsofbalancedvoltage
digitalinterfacecircuits
ITUTRecommendationV.11
(Previously“CCITT
Recommendation”)
(03/93)
Electricalcharacteristicsforbalanceddouble
currentinterchangecircuitsoperatingatdata
signallingratesupto10Mbit/s
NOTE This document is technically equivalent to
ANSI/TIA/EIA/422B1994.
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3
Terms, definitions and abbreviated terms
3.1 Terms from other standards
ForthepurposeofthisStandard,thetermsanddefinitionsfromECSSST0001
apply.
3.2 Terms specific to the present standard
3.2.1 accuracy
closenessofameasurementtotheactualquantitybeingmeasured
NOTE ForthepurposesofthisStandarditisexpressedas
percentageofthefullmeasurementrangeorasan
absolutevalue.
3.2.2 circuit
conducting path which conveys a signal across the interface from the signal
sourcetothesignaldestination
NOTE A circuit includes the cable conductor, any
intervening connectors, and any circuit elements
such as protection resistors and coupling
capacitors,whichmakeupthesignalpath.
3.2.3 DHS data interchange bus
underlyingcommunicationmediumwhichconnectstheDHScoreelements
NOTE Thiscanconsistofmorethanonephysicalbus.
3.2.4 DHS core element
componentofadatahandlingsystemwhichhasadirectconnectiontotheDHS
datainterchangebus
NOTE E.g.:buscontrollersandremoteterminals.
3.2.5 DHS peripheral element
componentofadatahandlingsystemwhichdoesnothaveadirectconnection
totheDHSdatainterchangebus
NOTE E.g.:sensorsandactuators.
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3.2.6 ground displacement voltage
voltagedifferencebetweensourceandreceivergroundreferences
NOTE Usersareencouragedtousethisdefinitioninstead
of‘commonmodevoltage’thatisnotcorrectwhen
referringtotheacademicdefinition.
3.2.7 time reference point
pointatwhichatimeintervalstartsorends
NOTE Itisthe midpointbetween the nominalhighand
nominallowsignalvoltages.
3.3 Abbreviated terms
Forthepurposeofthisstandard,theabbreviatedtermsofECSSSST0001and
thefollowingapply:
Abbreviation Meaning
A/D
analoguetodigital
ADC
analoguedigitalconverter
ASM
analoguesignalmonitor
BDM
bileveldiscretemonitor
BSD
bidirectionalserialdigital
BSM
bilevelswitchmonitor
CM
commonmode
DHS
datahandlingsystem
HPC
highpowercommand
HCHPC
highcurrenthighpowercommand
HVHPC
highvoltagehighpower
command
ISD
inputserialdigital
LPC
lowpowercommand
LPCP
lowpowercommand,pulsed
LPCS
lowpowercommand,static
LSB
leastsignificantbit
LVHPC
lowvoltagehighpowercommand
MSB
mostsignificantbit
OBDH
onboarddatahandling
OSD
outputserialdigital
TSM
temperaturesensorsmonitor
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3.4 Conventions
3.4.1 Bit numbering convention
Themostsignificantbitofannbitfieldis:
numberedbit0(zero),
thefirstbittransmitted,and
theleftmostbitonaformatdiagram.
Theleastsignificantbitofannbitfieldis:
numberedbitn1,
thelastbittransmitted,and
therightmostbitonaformatdiagram.
ThisconventionisillustratedinFigure31.
Bit 0 (MSB)
Bit n-1 (LSB)
First Bit Transmitted
n-bit Data Field
Figure31:Bitnumberingconvention
3.4.2 Timing diagram conventions
Timingdiagramsarealwaysdrawnwiththeearliesttimeontheleftandtime
advancingtotheright.
Whereanevent,suchasatransition,inonesignalcausesaneventinanother,
thetwoeventsarelinkedbyanarrowwiththetailofthearrowonthecausal
event
andtheheadofthearrowontheresultantevent.
Whereanevent inonesignalistheresultofaneventinanothersignalanda
qualifying condition in one or more other signals, the connecting arrow is
associatedwiththegoverningconditionusingabull’seye.
Theseconventions,
togetherwithothertimingdiagramsymbols,areshownin
Figure32.
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Figure32:Timingdiagramconventions
3.4.3 Signal and signal event naming convention
Signalsarenamedinamannerwhichindicatesthefunctionofthatsignal.For
example,aclockusedfordatabitsamplingcanbecalledDATA_CLK.
Control signal naming is meaningful with the function of the signal, its
direction,anditsassertionlevelsallindicated.The directionis indicatedwith
respect
totheDHScoreelementsothatanOUTsignalisanoutput,i.e.driven
from the core element. An IN signal is an input to the core element. For
example,asignalcarryingdataoutofthecoreelementisnamedDATA_OUT.
Control signal assertion or validity levels are
indicated within brackets. For
example, a gate output signal which is asserted when low is named
GATE_OUT(L).Similarly,aninputsignalwhichindicatesthatadeviceisready
whenitishighisnamedREADY_IN(H).
Signaleventssuchastransitionsandpulsesarealsonamedsymbolicallyusing
UPandDOWNindication.Forexample,STARTUPindicatesarisingedgeevent
on the start signal, and STOP
DOWN indicatesa falling edge on the stop signal.
RUN
UPDOWN indicates a positive going pulse on the run signal, while
HALT
DOWNUPindicatesanegativegoingpulseonthehaltsignal.
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3.4.4 Signal timing and measurement references
Signalriseandfalltimes,whichareshowninFigure33,aremeasuredbetween
10% and 90% of the difference between the nominal low and nominal high
signalvoltages,asitcanbeseeninthementionedfigure.
t
rise
t
fall
10%
50%
90%90%
50%
10%
Timing Reference Points
Figure33:Signaltimingandmeasurementreferences
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4
General
4.1 Introduction
Thisstandarddefineselectricalinterfacesforuseonboardspacecrafttoconnect
simpledevicessuchassensorsandactuatorstothedatahandlingsystem.The
interfacesdefinedare:
analoguesignalinterfaces(clause5)
analoguesignalmonitor
temperaturesensormonitor
bileveldiscreteinputinterfaces(clause6)
bileveldiscretemonitor
bilevelswitchstatusmonitor
commandinterfaces(clause7)
highpowerpulsecommand
lowpowercommand
serialdigitalinterfaces(clause8).
Eachinterfaceisdefinedintermsoftheelectricalandtimingcharacteristicsof
the signals comprising that interface. Connectors for the interfaces are not
defined because these are often highly project dependent. Cabling
characteristicsaredefinedwhereappropriate.
For the serial digital
interfaces, the data content of the digital words is not
definedsincethis isthesubject of higher level protocolstandards beyondthe
scopeofthisStandard.
Unless otherwise stated, specified performances are applicable when both
sourceandreceiverarepowered.
4.2 Architectural concepts
4.2.1 Overview
The interfaces specified in this Standard are intended to connect DHS core
elementsto DHSperipheralelements as showninFigure41.However, there
are no technical reasons to prevent these interfaces being used between core
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elementswhereitisappropriatetodoso,andthisStandarddoesnotpreclude
suchaconfiguration.
A peripheral element can have more than one user interface and also user
interfacesofdifferenttypes,dependingonitsfunctionanddesign.Forexample,
somesensorscansetthresholdlevelsorsensitivitiesby
meansofdatawrittento
them.Inthiscasethatsensorcanuseanoutputserialdigitalinterfacetowrite
thedatainadditiontoaninputserialdigitalinterfacetoreadthesensorvalue.
Alternatively,somedevicesaresignalledtoindicatethattheyarecommanded
to acquire a data
sample. In that case they can use a serial digital interface
togetherwithapulseinterface.
Figure41:Architecturalcontextofinterfacesdefinedinthisstandard
4.2.2 General failure tolerance
4.2.2.1 Input interfaces
a. Amongotherfailurecases,receiversshall:
1. Notbestressedandnotshowdegradedperformancewheninput
isopencircuitexceptontheinputI/Fthatisopencircuit.
2. Notbestressedandnotshowdegradedperformancewheninput
is short circuit to ground except on the input I/F
that is short
circuit.
NOTE Nospecificperformance requirementsare
imposedwhileinthisstatus.
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4.2.2.2 Output interfaces
a. Amongotherfailurecases,transmittersshall:
1. Notbestressedandnotshowdegradedperformancewhenoutput
isopencircuitexceptontheoutputI/Fthatisopencircuit.
2. Notbestressedwhenoutputisshortcircuittoground.
NOTE No specific performancesrequirementis imposed
whilein
thisstatus.
4.2.3 Interface control during power cycling
4.2.3.1 Input interfaces
a. Inputinterfacesshall notbedamagedor harmedduring powercycling
conditionstakingthetransmittingsidestateintoaccountinanynormal
stateorapplicablefailurecondition.
b. Receiversshallnotdeliverpowertotheothercircuitsorbestressedwhen
theunitisOFFwhileconnectedtoanactive
driver.
NOTE Nospecificperformance requirementsare
imposedwhileinthisstatus.
4.2.3.2 Output interfaces
a. Outputinterfacesshallnotbedamagedorharmedduringpowercycling
conditions when the receiving side state is in any normal state or
specifiedfailurecondition.
NOTE Nospecificperformance requirementsare
imposedwhileinthisstatus.
b. Forpulsecommandsitshallbeensuredthatspuriouscommandsare
not
emitted during power cycling that exceed activation limits for the
receivers.
NOTE1 Forpulsecommands,seeClause7.
NOTE2 This requirement does not specify the prevention
ofspuriouspulses,butensureseitherthat:
spuriouspulsesarebelowthethresholdforthe
receiver,or
the spuriouspulse
durationis shortenoughto
notdrivetheloadintoactivation(forexamplea
relaycoiloroptocouplerdiode).
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4.2.4 Cross-strapping
4.2.4.1 General
a. For 2 units (UNIT_1 & UNIT_2), that can be used in redundancy, the
crossstrapping of drivers and receivers shall be as specified in Figure
42,andmeetthefollowingconditions:
1. TheUNIT_2_AI/Fiscapabletoreceive:
(a) AsignalfromtheUNIT_1_AI/Fthroughadedicated
link
(b) AsignalfromtheUNIT_1_BI/Fthroughadedicatedlink
2. TheUNIT_2_BI/Fshalliscapabletoreceive:
(a) AsignalfromtheUNIT_1_AI/Fthroughadedicatedlink
(b) AsignalfromtheUNIT_1_BI/Fthroughadedicatedlink
3. TheUNIT_1_AI/Fiscapableto
deliver:
(a) AsignaltotheUNIT_2_AI/Fthroughadedicatedlink
(b) AsignaltotheUNIT_2_BI/Fthroughadedicatedlink
4. TheUNIT_1_BI/Fiscapabletodeliver:
(a) AsignaltotheUNIT_2_AI/Fthroughadedicatedlink.
(b) AsignaltotheUNIT_2_BI/Fthrougha
dedicatedlink.
b. To achieve full crossstrapping benefits, in terms of reliability, any
potential common failure of UNIT_1_A and UNIT_1_B drivers and
UNIT_2_AandUNIT_2_Breceiversshallbeavoided.
1_A_A
UNIT_1_A
D
UNIT_1
D
1_A_B
1_B_B
UNIT_1_B
D
D
1_B_A
2_A_A
UNIT_2_A
R
UNIT_2
UNIT_2_B
2_A_B
R
2_B_B
R
2_B_A
R
D = Driver
R = Receive
r
Figure42:Generalschemeofredundantunit’scrossstrapping
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4.2.4.2 Immunity at UNIT_2 level
a. Under the condition (Receiver = ON linked to Transmitter = OFF of
UNIT_1),intheconfigurationwhereUNIT_1driverisOFFandUNIT_2
receiverisON,theinformationreceivedbythisreceivershallnotdisturb
the valid information received by the other receiver (linked to a
TransmitterON).
NOTE
Inthisconfigurationtheelectricalstatusatreceiver
output is stable (due to hysteresis) but possibly
unknown(logicalʺ1ʺorʺ0ʺ).
b. Itshouldbeensuredthatanyinputsignalisinaknown(inactive)stable
statewhendriverisOFF.
c. If4.2.4.2bisnotmet,avalidation/
inhibitionstageatthereceiveroutput
ofUNIT_2shouldbeimplemented.
NOTE For example, the validation of the path can be
made by a dedicated direct command arriving
fromUNIT_1,whichinhibitstheUNIT_2receiver
output unused (if such a configuration has been
thoroughlydesignedwithrespecttofailurecases).
4.2.4.3 Protections at UNIT_1 driver level
a. Under the condition (Transmitter = OFF linked to Receiver = ON of
UNIT_2),whetherpoweredor not,UNIT_1 driversshall withstand any
receivercharacteristicsasdescribedinClauses5to8.
4.2.4.4 Protections at UNIT_2 receiver level
a. Under the condition (Receiver = OFF linked to Transmitter = ON of
UNIT_1),whetherpoweredornot,UNIT_2receiversshallwithstandany
drivercharacteristicsasdescribedinClauses5to8.
4.2.5 Harness cross-strapping
4.2.5.1 Overview
Harnesscrossstrappingisappliedwhenheritageunits,withoutclassicalcross
strapping interfaces, are used, in the case that a single redundant unit is
interfacedtobothanominalandredundantsystem. Ifthespacecraftisseverely
masslimited,harnesscrossstrappingcanbeusedinstead.
Harnesscrossstrappingcanbe
usedintwoconfigurations:
SinglesourceDualreceiverconfiguration,asshowninFigure43.
DualsourceSinglereceiverconfiguration,asshowninFigure44.
The Single source Dual receiver configuration is typically applied for BSM
interfacesasdescribedinclause6.2.
The Dual
source Single Receiver configurationis typically applied for HPC
interfacesasdescribedinclause7.1.
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Note that this harness crossstrapping can be performed by galvanic
connectionsinharness,asindicatedinFigure43andFigure44.However,the
equivalent configuration applies in case the physical interconnection is
performedeitherwithinthesourceorwithinthereceiverunit.Thegeneralrules
andprotections
asmentionedinthisclause4.2.5applythenalsoforthosecases.
Possible problems that can be introduced by harness crossstrapping include
failure propagation, loading and leakage injection of the active I/F by the
redundant, inactive circuit such that the active circuit does not meet its
performance requirements, incompatibility
of protection circuitry of a given
circuit with either the Receiver I/F circuit or the Driver (see Figure 44) I/F
circuit. Note that in general it is important to consider loading by the
redundant,inactivecircuitalsowhenpoweredoff,eveniftheinactivecircuitis
normallypowered(hotredundancy).
1_A
UNIT_1_A
D
UNIT_1
1_B
UNIT_1_B
D
2_A_A
UNIT_2_A
R
UNIT_2
UNIT_2_B
2_A_B
R
2_B_B
R
2_B_A
R
D = Driver
R = Receiver
Figure43:ExampleschemeforSinglesourceDualreceivercrossstrapping
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1_A_A
UNIT_1_A
D
UNIT_1
D
1_A_B
1_B_B
UNIT_1_B
D
D
1_B_A
2_A
UNIT_2_A
R
UNIT_2
UNIT_2_B
2_B
R
D = Driver
R = Receiver
Figure44:ExampleschemeforDualsourceSinglereceivercrossstrapping
4.2.5.2 Provisions
a. Ifharnesscrossstrappingisused,thereshallbenomechanismwhereby
thefailureofeitherthereceiverorunitinterfacecanpropagatetotheI/F
ofanother,unrelatedunit.
NOTE Thisrequirementreferstoacommonmodefailure
where a failure of one interface then propagates
inside the
receiver thereby affecting units
unrelatedtotheoriginalfailure.
b. If harness crossstrapping is used,the calculation of the overall system
reliabilityshallincludethepotentialdegradationordamageoftheI/Fof
aredundantunitduetothefailureofotherinterface.
NOTE Thisrequirementreferstothe
failureonanominal
unit causing the inoperability of the crossstrap.
Thismeansthatthereisareductioninthepossible
reliabilityofthecrossstrap.
c. Ifharnesscrossstrappingisused,thecapabilityshallbeprovidedtoshut
downtheinoperableunitregardlessofthefailuremode
NOTE
Thisimpliesthatthepowercanberemovedfrom
the unit by independent means such as disabling
thepowerinterfaceatthepowerdistributionunit
(e.g.withthemeansdescribedinclause4.2.4.2)
d. Under the condition (Transmitter = OFF linked to Receiver = ON of
UNIT_2),whetherpoweredor
not,UNIT_1driversshallwithstandany
receivercharacteristicsasdescribedinClauses5to8.
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e. Under the condition (Receiver = OFF linked to Transmitter = ON of
UNIT_1),whetherpoweredornot,UNIT_2receiversshallwithstandany
drivercharacteristicsasdescribedinClauses5to8.
4.2.6 Cable capacitance
It isimportant thatthe DHS interfacesconsider the capacitive loadingby the
harness.Figure45definesthecapacitancesinvolvedforatwistedshieldedpair
cable.
C1
C2 C2
Figure45:Cablecapacitancedefinitions
Effectivecapacitancescanthenbecalculatedaccordingto:
Coretocorecapacitance
2
2
1
C
CC
CC
+= 
Coretoshieldcapacitance
21
21
2
CC
CC
CC
CS
+
+=

Core to core capacitance with shield connected to one core
21 CCC
CT
+= 
Notethatthelattercaseappliestypicallywheneitherthesourceorthereceiver
issingleended,whichimpliesthatboththeshieldandoneofthecorewiresare
grounded.
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5
Analogue signal interfaces
5.1 Overview
Theanaloguesignalinterfacesareusedfordirectconnectiontoadevicewhich
produces a continuous variable analogue voltage to indicate the value of the
parameterbeingmeasured.
Usually,theanaloguevoltageproducedbythesensororaperipheralelementis
convertedintoadigitalvaluewithinthecoreelementto
whichitisconnected.
This Standard specifies the electrical characteristics of the analogue signal
interfaces.
Twotypesofanalogueinterfacesarespecified:
Analoguesignalmonitorinterface,ASM(see5.2)
Temperaturesensorsmonitorinterface,TSM(see5.3)
5.2 Analogue signal monitor (ASM) interface
5.2.1 General
5.2.1.1 Overview
The analogue signal monitor interface is based on differential receiver circuit
whereboththehighandlowanaloguesignallinesarefloatingwithrespectto
the receiver signal ground; the source interface can be either single ended or
differential.
Theanaloguevoltageprovidedissampledintermittentlyby the coreelement.
The
precisefrequencyandthedurationofthesamplingintervaldependonthe
A/D conversion service being used. However, the input impedance and
capacitanceexhibitedbyananaloguesignalinterfacecandifferwhentheinput
signal is actually being sampled compared with when it is not. As a
consequence, different input
impedance and capacitance requirements are
providedforthedifferentconfigurations.
In addition, the impedanceseen when the receiver element is powered off is
specified.
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5.2.1.2 Basic application scenario
Theinterfacespecifiedinthisclause5.2.1.2is definedonthe basisofatypical
analoguesignalmonitoringapplicationscenario,i.e.
differentialvoltagerange:0to5Voroptionally0to5,12V;
signalbandwidth:≤1Hz;
NOTE This means that accuracy requirements are
specified here assuming only slowly changing
(quasistatic) signals. That does not prohibit, for
instance,rapidtransitionsin signals,but accuracy
isunspecifiedduring
suchevents.
grounddisplacementvoltage:≤±1Vinthefrequencyrange0to1kHz,
fallingat20dBperdecadeupto1MHz;
conversionresolution:12bits.
NOTE1 Thespecified12bitsresolutionisnotincompatible
with use of ADC having 14 or even 16 bits
resolution.Inthatcase,LSBareʺnotsignificantʺ.
NOTE2 Even if the overall channel accuracy requirement
in5.2.1.4canbemetalso with an8bitADC,itis
important to note that in this case the ADC
quantizationerrorcontributes±0,2%totheoverall
channelaccuracy,
thusnormallyagoodpracticeis
tousea12bitADC.
5.2.1.3 Applications other than the basic scenario
a. Iftheactualscenariodiffersfromtheonedefinedin5.2.1.2,theinterface
shallnotbedirectlyused.
NOTE1 Forexample,ifthespecificapplicationuseshigher
conversion accuracy or hasdifferent operational
conditions,e.g.higherdisplacement.
NOTE2 Inparticular,grounddisplacementheavilyaffects
the achievable conversion accuracy.
Different
scenario or specified performances can, for
instance,askforsourceimpedancebalancing.
b. The modifiedinterface shall be supportedby an analysis ofthe overall
system, including both interface source and receiver as well as
interconnectingwiring.
5.2.1.4 Acquisition of the analogue channels by the core
element
a. The errors introduced by the DHS receiver analogue acquisition chain,
including temperature, ground displacement voltage rejection, A/D
conversion inaccuracy, herein specified source impedance and cable
capacitance,supplyvoltagevariations,lifetimeandradiationeffectsshall
belessthan1%ofthefullscale.
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5.2.2 Analogue signal monitor interface
5.2.2.1 Source circuit
a. ThesourcecircuitshallmeetthecharacteristicsspecifiedinTable51.
Table51:Analoguesignalmonitorsourcecircuitcharacteristics
ReferenceCharacteristic Value
5.2.2.1a.1 Circuittype Singleendedordifferential
5.2.2.1a.2 Transfer DCcoupled
5.2.2.1a.3 Zeroreference
Signalgroundincaseofdifferentialsource
(refFigure52),thereturnsignal’spotential
shallbeequaltounit’schassisground.
5.2.2.1a.4(a) 0Vto+5V
a
5.2.2.1a.4(b)
Nominaloutputvoltagerange,V
out
0Vto+5,12V
5.2.2.1a.5 Outputimpedance,Zout 5kΩ
5.2.2.1a.6 Faultvoltagetolerance,Vsft
17,5Vto+17,5Vwithanovervoltagesource
impedance>1,0kΩ
5.2.2.1a.7 Faultvoltageemission,Vsfe‐16,5Vto+16,5V
a
Therange0V5Visthepreferredone.5,12VcanbeusedifstraightforwardA/Dconversionisnecessary.
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5.2.2.2 Receiver circuit
a. ThereceivercircuitshallmeetthecharacteristicsspecifiedinTable51.
Table52Analoguesignalreceivercircuitcharacteristics
Reference Characteristic Value
5.2.2.2a.1 Circuittype Differential
5.2.2.2a.2 Transfer DCcoupled
5.2.2.2a.3(a) differential:0Vto+5V
a
5.2.2.2a.3(b)
Nominalinputvoltagerange,V
in
differential:0Vto+5,12V
5.2.2.2a.4 Grounddisplacementvoltage,VGD
1Vto1Vupto1kHzrollingoffat
20dB/decadeupto1MHz
5.2.2.2a.5 Differentialinputimpedance(sampling),Zis 1MΩ
5.2.2.2a.6
Differentialinputimpedance(notsampling),
Z
ins
10MΩ
5.2.2.2a.7
Differentialinputimpedance(poweredoff),
Z
ioff
10kΩ
5.2.2.2a.8 Differentialinputcapacitance(sampling),Cis1,5μF
5.2.2.2a.9
Differentialinputcapacitance(notsampling),
C
ins
1,5μF
5.2.2.2a.10
Differentialinputcapacitance(poweredoff),
C
ioff
1,5μF
5.2.2.2a.11 Faultvoltageemission,Vrfe
16,5Vto+16,5Vwithaseries
impedance1,0kΩ
5.2.2.2a.12 Faultvoltagetolerance,Vrft‐17,5Vto+17,5V
a
Therange0V5Visthepreferredone.5,12VcanbeusedifstraightforwardA/Dconversionisnecessary
NOTE Whenprimeand(cold)redundantconfigurationsareusedandimplementedbycrossstrappingas
definedinclause4.2.5,careshouldbetakentoensurethattheimpendence
oftheoffdevicedoesnot
undulyinfluencethatofthepowereddevice.
5.2.2.3 Harness
5.2.2.3.1 Wire type
a. Thewiretypeshouldbetwistedshieldedlines.
b. If5.2.2.3.1aisnotmet,ntuplesshallbeused.
c. Theshieldshallbeconnectedtothestructuregroundbothonsourceand
receiversides.
5.2.2.3.2 Core to shield capacitance
a. ThecapacitanceCCTshallbelessthan2nF.
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5.2.2.4 Interface arrangement
The electrical interface arrangement is depicted in Figure 51 and Figure 52,
which show specific implementation to be taken as examples, but other
implementationscomplianttorequirementsarenotexcluded.
V
+
V
+
SOURCE
RECEIVER
Figure51:Analoguesignalmonitor(singleendedsource)
interfacearrangement
V+
V+
SOURCE
RECEIVER
V-
V-
-
+
Figure52:Analoguesignalmonitor(differentialsource)
interfacearrangement
5.3 Temperature sensors monitor (TSM) interface
5.3.1 Overview
Temperature monitor channels are resistance measurement channels used for
resistivetemperaturesensoracquisition.
The wordʺthermistorʺ is derived from the descriptionʺthermally sensitive
resistorʺ. Thermistors are further classified asʺPositive Temperature
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Coefficientʺ devices (PTC devices) orʺNegative Temperature Coefficientʺ
devices(NTCdevices):
PTCdevicesaredeviceswhoseresistanceincreasesastheirtemperature
increases.
NTCdevicesaredeviceswhoseresistancedecreasesastheirtemperature
increases.
Twotypesoftemperaturemonitorchannelsareaddressedherein,referringto
thetwomainclassesof
transducersavailableonthemarket:
TSM1: Wide range resistance acquisition, suitable for NTC thermistors
(negativetemperaturecharacteristic).
TSM2: Limited range resistance acquisition, suitable for platinum (PT)
type.
The conditioning configuration to be used depends on the transducer used.
Both TSM1 and TSM2 interfaces are specified in terms of
resistance
measurementaccuracy.
NOTE TSM1canbeusedforplatinumtypesensors(PT),
but that generally shows worse accuracy than a
well adapted TSM2. Also, TSM2 can be used for
NTC type of sensor, butthe temperaturerangeis
thenrestricted.
Examples of corresponding measurement error in terms of temperature
are
giveninclause5.3.5.5.
5.3.2 TSM acquisition layout
a. Thethermistorsshallbepoweredbythereceiver,and
b. The resulting voltage shall be utilised to feed a dedicated analogue
channel.
NOTE The objective of these requirements is that the
receiverisabletodirectlyinterfacewithapassive
thermistor:
5.3.3 TSM acquisition resolution
a. Atleast12bitresolutionshallbeused.
NOTE Even if the overall channel accuracy requirement
canbemetalsowithan8bitADC,itisimportant
tonotethatinthiscasetheADCquantizationerror
alone contributes ±0,2% to the overall channel
accuracy.
5.3.4 TSM wire configuration
a. Dedicated input and return line from the current source to each
thermistorchannelshallbeprovided.
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5.3.5 TSM electrical characteristics
5.3.5.1 TSM1
5.3.5.1.1 Overview
TheTSM1interfacehasthefollowingfeatures:
Themeasurableresistancerangeisspecifiedfrom0to∞ Ω.
TheinterfaceisnormalizedwithaparameterR
NORM(Ω),selectablewithin
a specific range, where R
NORM is the resistance of the thermistor at a
specifiedtemperature point, where the highest temperature
measurementaccuracyisneeded(thecentreofthemeasurementrange).
NOTE R
NORM is selected per group of channels as a
function of the sensor type and the temperature
rangeofinterest.
Thespecifiedaccuracyisexpressedasamaximumerror±Δx.
Thespecifiedaccuracyintermsofresistanceisobtainedfromaformula
includingR
NORMandΔx.
The resistance accuracy is specified at the DHS unit terminals, i.e.
excludinganyerrorcontributionfromthethermistororharness.
5.3.5.1.2 TSM1 error model
a. ThemaximumerrorinRth,ΔRth,shallbecalculatedasfollows:
x
RRxR
RR
R
NORMthNORM
NORMth
th
Δ
+Δ
+
=Δ
)(
)(
2
, ifRNORM>Δx(Rth+RNORM),
=Δ
th
R otherwise
NOTE ThiscalculationisbasedonthemodeloftheTSM1
interface shown in Figure 53. R
th(T) symbolizes
the resistance of the thermistor as a function of
temperatureT.
TheoutputfromtheADC,x,hastherange0to1.
Theformulato expressxasafunctionofR
th(T)is
then:
NORMth
th
ref
in
RTR
TR
V
V
x
+
==
)(
)(
Figure 54 shows how the relative error in R
th,
ΔR
th/Rth, varies with Rth with examples of RNORM
andΔx.
Examples have been evaluated for some specific
thermistor types in clause 5.3.5.5, showing the
errorintermsoftemperature.
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+
Vcond
R
NORM
R
th
(T)
x +
x
ADC
Vref
Vin Vout
x
x
Figure53:TSM1referencemodel
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
1.E+02 1.E+03 1.E+04 1.E+05
Rth
deltaRth/Rth
Rnorm=1kohm, deltax=0,01
Rnorm=10kohm, deltax=0,01
Rnorm=1kohm, deltax=-0,01
Rnorm=10kohm, deltax=-0,01
Figure54:RequirementforΔRth/RthasafunctionofRNORMandRth.Δx=±0,01
5.3.5.1.3 TSM1 source electrical characteristics
a. ThecharacteristicsinTable53shallbeprovided.
Table53:TSM1sourcecircuitcharacteristics
Reference Characteristic Value
5.3.5.1.3a.1 Circuittype FloatingResistivesensor
5.3.5.1.3a.2 Transfer DCcoupled
5.3.5.1.3a.3 Resistancerange,Rs 0toΩ
5.3.5.1.3a.4 Faultvoltagetolerance,Vsft‐17,5Vto+17,5Vwithanovervoltagesource
impedance≥1kΩ
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5.3.5.1.4 TSM1 receiver electrical characteristics
a. ThecharacteristicsinTable54shallbeprovided.
Table54:TSM1receivercircuitcharacteristics
Reference Characteristic Value
5.3.5.1.4a.1 Circuittype
Singleendedreceiverwithmultiplexed
inputs
5.3.5.1.4a.2 Transfer DCcoupled
5.3.5.1.4a.3 Sensorinjectedpower,Pi≤1mW
5.3.5.1.4a.4 Measurementerror,Δx <±0,01
5.3.5.1.4a.5 Parameterizedresistancerange,RNORM
1kΩ,to10kΩ,tobespecifiedpergroup
ofchannels
5.3.5.1.4a.6 Faultvoltageemission,Vrfe
16,5Vto+16,5Vwithasource
impedanceof≥1kΩ
5.3.5.1.4a.7 Faultresistancetolerance,Rrft Shortcircuittoground
NOTE The low resistance range of RNORM is suitable for TSM receiver systems using power switched
thermistorconditioning,wherelowimpedanceisofspecialinteresttoachievefastsettling.
The high resistance range of R
NORM is more suitable for TSM receiver systems using continuous
thermistorconditioning,wherelowpoweriscrucial,butfastsettlingisoflessconcern
5.3.5.1.5 Harness
a. Thewiringtypeshallbetwistedn–tuple.
b. Thecapacitance C
CCmeasuredbetween the twocorewires shallbe less
thanorequalto1nF.
5.3.5.1.6 Interface arrangement
TheelectricalI/FarrangementisspecifiedinFigure55.
NOTE1 Circuitry and resistors are indicative only; other
implementations meeting the above requirements
arenotexcluded.
NOTE2 In practical implementations a resistance to
groundinthereceiverisoftenused.
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SOURCE
RECEIVER
MUX A
NTC
Thermistor
Figure55:TSM1interfacearrangement
5.3.5.2 TSM2
5.3.5.2.1 Overview
TheTSM2interfacehasthefollowingfeatures:
Themeasurableresistancerangeisspecifiedfrom0ΩtouptoR
MAX.
NOTE R
MAXcanbeseenasthemaximumresistanceofthe
thermistorinthetemperaturerangeofinterest.
R
MAX can be chosen as characteristic of a group of channels within a
specificrange.
Thespecifiedaccuracyisexpressedasamaximumerror±Δx.
ThespecifiedaccuracyintermsofresistanceisexpressedasΔxR
MAX.
The resistance accuracy is specified at the DHS unit terminals, i.e.
excludinganyerrorcontributionfromthethermistororharness.
5.3.5.2.2 TSM2 error model
a. ThemaximumerrorinRth,ΔRth,expressedasafunctionofΔx,shallbe:
xRR
MAXth
Δ
=
Δ
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5.3.5.2.3 TSM2 source electrical characteristics
a. ThesourceshallmeetthecharacteristicsspecifiedinTable55.
Table55:TSM2sourcecharacteristics
Reference Characteristic Value
5.3.5.2.3a.1 Circuittype FloatingResistivesensor
5.3.5.2.3a.2 Transfer DCcoupled
5.3.5.2.3a.3 Resistancerange,Rs
0ΩtoR
MAX
Rsisselectedpergroupofchannelsasafunctionof
thesensortypeandthetemperaturerangeofinterest
5.3.5.2.3a.4 Faultvoltagetolerance,Vsft
17,5Vto+17,5Vwithanovervoltagesource
impedance≥1kΩ
5.3.5.2.4 TSM2 receiver electrical characteristics
a. ThereceivershallmeetthecharacteristicsspecifiedinTable56.
Table56:TSM2receivercharacteristics
Reference Characteristic Value
5.3.5.2.4a.1 Circuittype Singleendedreceiverwithmultiplexedinputs
5.3.5.2.4a.2 Transfer DCcoupled
5.3.5.2.4a.3 Sensorinjectedpower,Pi≤1mW
5.3.5.2.4a.4 Measurementerror,Δx <±0,01
5.3.5.2.4a.5
Parameterizedresistance
range,R
MAX
1kΩto5kΩ,tobespecifiedpergroupofchannels
5.3.5.2.4a.6 Faultvoltageemission,Vrfe
16,5Vto+16,5Vwithasourceimpedanceof≥1,0
kΩ
5.3.5.2.4a.7 Faulttolerance,Rrft Shortcircuittoground
5.3.5.3 Harness
5.3.5.3.1 Wire type
a. Thewiretypeshallbetwistedntuple.
5.3.5.3.2 Core to core capacitance
a. ThecapacitanceCCCmeasured between thetwocorewires shall be less
thanorequalto1nF.
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5.3.5.4 Interface arrangement
TheelectricalinterfacearrangementisspecifiedinFigure56.
NOTE Circuitryisindicativeonly;otherimplementations
meetingtheaboverequirementsarenotexcluded.
SOURCE
RECEIVER
MUX A
PT1000
Figure56:TSM2interfacearrangement
5.3.5.5 TSM examples
5.3.5.5.1 TSM1 examples
Allthermistorsof NTCtypeshowaquasiexponentialtemperaturesensitivity
inΔR
th/Rthofroughly4 %/°Cor onedecade per 60 °C. Thatmeans that when
using an NTC thermistor for a TSM1 channel, Figure 54 can be used as a
generalindicationofaccuracyintemperatureby:
rescalingtheyaxisbyafactor1°C/0,04,
exchanging
thelogarithmicxaxiswithalineartemperaturescalewhere
minimum point of |ΔR
th/Rth| is set to thermistor temperature at RNORM
andonedecadecorrespondsto60°C.
4K3A354 (ESCC Detail Specification No. 4006/013, variant 04) is a thermistor
withnominally4kΩresistanceat25°C.Figure57showstemperatureaccuracy
specifically of a 4K3A354 thermistor connected to a TSM1 channel specified
withRNORM=4kΩ.
Thefiguredoesnotincludeanyinaccuracyofthesensor
itself
YSI44907isathermistor with nominally10kΩresistanceat25°C.Figure58
showstemperatureaccuracyspecificallyofaYSI44907thermistorconnectedto
aTSM1channelspecifiedwithRNORM=10kΩ.
Asshownin
thetwoexamples,theaccuracyintermsoftemperaturebecomes
quitesimilarfordifferentNTCthermistortypes,providedthatR
NORMisselected
pertypeforthesametemperaturerange.
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-10
-8
-6
-4
-2
0
2
4
6
8
10
-60 -40 -20 0 20 40 60 80 100
T(degrC)
Temp error
(degrC)
Rnorm=4kohm, deltax=0,01
Rnorm=4kohm, deltax=-0,01
Figure57:ExampleTSM1and4K3A354thermistor
-10
-8
-6
-4
-2
0
2
4
6
8
10
-60 -40 -20 0 20 40 60 80 100
T(degrC)
Temp error
(degrC)
Rnorm=10kohm, deltax=0,01
Rnorm=10kohm, deltax=-0,01
Figure58:ExampleTSM1andYSI44907thermistor
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5.3.5.5.2 TSM2, PT1000
Theplatinumtemperaturesensorsshowfairlyconstanttemperaturesensitivity
inR
thofroughly0.004R0/°C,whereR0isthenominalresistance(at0°C).
PT1000isaplatinumsensorwithnominally1000Ωresistanceat0°C.Figure59
shows temperature accuracy specifically of a PT1000 connected to a TSM2
channel specified with R
MAX = 1700 Ω. The figure does not include any
inaccuracyofthesensoritself.
R
MAX = 1700 Ω for the PT1000 sensor covers the temperature range up to
+183°C.
-10
-8
-6
-4
-2
0
2
4
6
8
10
-150 -100 -50 0 50 100 150
Temp (degrC)
Temp error
(degrC)
Rmax=1700, deltax=0,01
Rmax=1700, deltax=-0,01
Figure59:ExampleTSM2andPT1000thermistor
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6
Bi-level discrete input interfaces
6.1 Bi-level discrete monitor (BDM) interface
6.1.1 Overview
The bilevel discrete monitor (BDM) interfaces are used for reasonably static,
discrete status and telemetry monitoring by the core element. The monitored
signal is bilevel discrete in that it can take only two values, high or low,
indicatedbythesignalvoltage.
The bilevel discrete interface consists of
a signal, BL_DATA_IN, which is
generatedbytheperipheralelement.Thissignalissampledperiodicallybythe
coreelement.
In a practical implementation, a number of bilevel discrete interfaces can be
aggregatedtoformamultiplebitdatawordinthecoreelement.
Thebilevel discreteinputinterface
consistsof asignal, BL_DATA_IN, which
canassumetwovalues,highorlow,withrespecttothesignalreference.This
signal is maintained continuously by the peripheral element and can be
sampledatanytimebythecoreelement.
On sampling, the coreelement encodes the BL_DATA_INvalue into a single
binarybitofdatawhichcanbeembeddedinalargerdataword.
There are no timing parameters associated with this interface. The
BL_DATA_INsignalismaintainedcontinuouslybytheperipheralelementand
can generally be regarded as static. However, if the BL_DATA_IN signal is
sampledduringatransitionfrom
oneleveltotheother, theresultdetermined
bythecoreelementcanbeinvalid.
6.1.2 Bi-level discrete monitor interface
6.1.2.1 Bi-level discrete monitor input interface -
BL_DATA_IN signal
a. Theperipheralelementshall
1. provideaBL_DATA_INsignal,and
2. continually maintain such signal in one of two states, high
(logical‘1’)orlow(logical‘0’).
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6.1.2.2 BDM electrical characteristics
6.1.2.2.1 Source circuit
a. ThesourcecircuitshallmeetthecharacteristicsspecifiedinTable61.
Table61:BDMsourcecharacteristics
Reference Characteristic Value
6.1.2.2.1a.1 Circuittype Singleended
6.1.2.2.1a.2 Transfer DCcoupled
6.1.2.2.1a.3 Zeroreference Signalground
6.1.2.2.1a.4 Lowoutputvoltage,VLout 0Vto+0,5V
6.1.2.2.1a.5 Highoutputvoltage,VHout
2,4Vto+5,5V,
intoaloadof100kΩorgreater
6.1.2.2.1a.6 Outputimpedance,Zout 5kΩ
6.1.2.2.1a.7 Faultvoltageemission,Vsfe‐1Vto+7V
6.1.2.2.1a.8 Faultvoltagetolerance,Vsft
17,5Vto+17,5Vwithanovervoltagesource
impedanceof1,0kΩ
6.1.2.2.2 Receiver circuit
a. ThereceivercircuitshallmeetthecharacteristicsspecifiedinTable62.
Table62:BDMreceivercharacteristics
Reference Characteristic Value
6.1.2.2.2a.1 Circuittype Differentialreceiverwithmultiplexedinputs
6.1.2.2.2a.2 Transfer DCcoupled
6.1.2.2.2a.3
Lowleveldifferentialinput
voltage,V
Lin
0Vto0,9V
6.1.2.2.2a.4
Highleveldifferentialinput
voltage,V
Hin
2,0Vto5,5V
6.1.2.2.2a.5
Grounddisplacement
voltage,V
GD
1Vto1Vupto1kHzrollingoffat20dB/decadeup
to1MHz
6.1.2.2.2a.6 Inputimpedance,Zin
Duringacquisition:100kΩ
Outsideacquisition:100kΩ
DHSwithpoweroff:10kΩ
6.1.2.2.2a.7 Faultvoltageemission,Vrfe‐16,5Vto+16,5Vwithaseriesimpedanceof1,0kΩ
6.1.2.2.2a.8 Faultvoltagetolerance,Vrft‐2Vto+8V
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6.1.2.3 Harness
6.1.2.3.1 Wire type
a. Bothtwistedpairandtwistedshieldedpairlinesmaybeused.
b. Shields shall be connected to structure ground on source and receiver
side.
6.1.2.3.2 Core to shield capacitance
a. Ifshieldedpairisused, thecapacitanceCCSmeasuredbetweenthecore
wireandtheshieldshallbe2nF.
6.1.2.3.3 Core to core capacitance
a. Ifunshieldedpairisused,thecapacitanceCCCmeasuredbetweenthetwo
corewiresshallbe1nF.
6.1.2.4 Interface arrangement
TheelectricalinterfacearrangementisdepictedinFigure61.Thefigureshows
aspecificimplementationasexample,butotherimplementationsconformingto
therequirementsarenotexcluded.
V
+
V
+
SOURCE
RECEIVER
Figure61:BDMInterfaceconfiguration
6.2 Bi-level switch monitor (BSM) interface
6.2.1 General principles
The bilevel switch monitor (BSM) interface is used by the core element to
determine the status of a switch in the peripheral element. The peripheral
element of this interface is entirely passive, consisting only of a single pole
switchelectricallyisolatedfromallothercomponentsoftheperipheralelement.
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This interface is usedby the core element to determine the statusof switches
and relays in the peripheral element and has the advantage that it can be
operatedevenwhentheperipheralelementispowereddown.
Theswitchstatusinterfaceisentirelydrivenandoperatedbythecoreelement.
The
core element provides a continuous reference voltage signal, and
periodically samples the input signal and compares it to the reference. The
resultisencodedintoabinarybittoindicatewhethertheswitchwasclosedor
open.
Therearenotimingconstraintsrelatedtothisinterfacesincetheswitchstatus
being monitored is normally static or changing infrequently. However, if the
input signal is sampled while the switch status is changing, the result canbe
invalid.
Thesignal interfacereceiverissimilartoa bileveldiscrete(BDM)inputwith
thefollowingexceptions:
Groundisreferredtoreceiver(insteadof
source)ground.
Itisbiasedtoahighlevel,whenitisnotbeingdriven,bytheconnection
oftheinputtoareferencevoltagethrougharesistance.Whentheswitch
contact is closed, the inputsignal is forced to a low level by presented
lowimpedance.
The interface
receiver converts such input signal in one of two digital states,
high (logical ‘1’) for switch source open status, or low (logical ‘0’) for switch
sourceclosedstatus.
In case of specific needs, optocouplers can be used. In that case the specific
interfaces are defined on a system basis, thus
they are not covered by this
Standard.
6.2.2 Bi-level switch monitor interface
6.2.2.1 Source circuit
a. ThesourcecircuitshallmeetthecharacteristicsspecifiedinTable63.
Table63:Switchsourcecharacteristics
ReferenceCharacteristic Value
6.2.2.1a.1 Circuittype FloatingRelaycontact
6.2.2.1a.2 Transfer DCcoupled
6.2.2.1a.3 Operatingcurrent,Iop Upto10mA
6.2.2.1a.4 Operatingvoltage(opencircuit),Vop Upto15V
6.2.2.1a.5 Switchclosedresistance,RC 50Ω
6.2.2.1a.6 Switchopenresistance,RO 1MΩ
6.2.2.1a.7 Faultvoltagetolerance,Vsft
17,5Vto+17,5Vwithanovervoltagesource
impedanceof1,0kΩ
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6.2.2.2 Receiver circuit
a. ThereceivercircuitshallmeetthecharacteristicsspecifiedinTable64.
Table64:Switchreceivercharacteristics
ReferenceCharacteristic Value
6.2.2.2a.1 CircuitType Singleendedreceiverwithpullupresistor
6.2.2.2a.2 Transfer DCcoupled
6.2.2.2a.3 Zeroreference Signalground
6.2.2.2a.4 Outputcurrent,Iout 0,1mAto10mA(whencontactsclosed)
6.2.2.2a.5 Outputvoltage,Vout <15V(whencontactsopen)
6.2.2.2a.6 Faultvoltageemission,Vrfe‐16,5Vto+16,5Vwithasourceimpedanceof
1,0kΩ
6.2.2.2a.7 Faulttolerance,Vrft Shortcircuittoground
6.2.2.3 Harness
6.2.2.3.1 Wire type
a. Thewiretypeshallbetwistedn–tupletype.
6.2.2.3.2 Core to core capacitance
a. The capacitance CCC measured between the two core wires shall be
1nF.
6.2.2.4 Interface arrangement
The electrical interface arrangement is depicted in Figure 62, which shows
specific implementation to be taken as example, but other implementations
conformingtorequirementsarenotexcluded.
TP
TP
SOURCE
RECEIVER
MUX
V
+
Figure62:Switchstatuscircuitinterfacearrangement
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7
Pulsed command interfaces
7.1 High power command (HPC) interfaces
7.1.1 General principles
Thehighpowerpulse(HPC)commandinterfacesareintendedforloaddriving
interfacesand,forexample,canbeusedtoswitchrelaysorsimilarloads.The
highcurrentcapabilitiesoftheseinterfacesleadtotheirprotectionagainstshort
circuitingandagainstfailureinahighcurrentmode.
The high power pulse
command consists of a single signal, HPC_OUT(H),
generatedbythecoreelement.Thisisconnectedbyasingleendedcircuittothe
input at the peripheral element. The interface is entirely controlled from the
coreelement.
ThreeclassesofHPCaredefinedhere:
LVHPC:lowvoltageHPC
(clause7.1.3),
HVHPC:highvoltageHPC(clause7.1.4),and
HCHPC:highcurrentHPC(clause7.1.5).
7.1.2 High power command interface
7.1.2.1 High power pulse command - HPC_OUT(H) signal
a. Thecoreelementshall
1. provideanHPC_OUT(H)signal,and
2. drivesuchasignal.
7.1.2.2 High power pulse command - HPC_OUT(H) signal
passive state
a. ThepassivestateoftheHPC_OUT(H)signalshallbelow.
7.1.2.3 High power pulse command - HPC_OUT(H) signal
active state
a. TheactivestateoftheHPC_OUT(H)signalshallbehigh.
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7.1.2.4 High power pulse command output – driver
unpowered
a. TheHPC_OUT(H)outputsignalshallbeinpassivestatewhenthedriver
isunpowered.
7.1.2.5 High power pulse command output - failure mode
a. Thedesignofthehighpowerpulsecommandinterfaceshallensurethat
no failure mode results in the output being permanently active (high
state).
7.1.2.6 High power command configuration
a. The high power discrete pulse command source shall be referenced to
sourcesignalground.
b. Thelo
adshallbeisolatedfromanyuserelectricalreference.
7.1.2.7 High power command transient protection
a. Both the high power pulse command source and receiver shall be
equippedwithcircuitstosuppressanyswitchingtransients.
NOTE This is particularly important to suppress
transients due to inductive loads such as relays,
whichcancausethecurrentdrivecapability,orthe
overvoltage capability of the source to
be
exceeded.
7.1.2.8 High power command short circuit protection
a. The high power pulse command source shall be short circuit proof for
shortcircuitstosourceorreceiversignalgroundandstructure.
7.1.3 Low voltage high power command (LV-HPC)
electrical characteristics
7.1.3.1 Source circuit
a. ThesourcecircuitshallmeetthecharacteristicsspecifiedinTable71.
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Table71:LVHPCsourcecharacteristics
ReferenceCharacteristics Value
7.1.3.1a.1 Circuittype Singleendeddriverreturnoverwire
7.1.3.1a.2 Transfer DCcoupled
7.1.3.1a.3 Activestateoutputvoltage,VAout 12Vto16V
7.1.3.1a.4 Passivestateoutputleakagecurrent,IPout <100μA
7.1.3.1a.5 Pulsewidth,tP
4msto1024ms(systemdesign
selectabledependingonreceiver
characteristics)
7.1.3.1a.6 Outputvoltageriseandfalltimes,tr,tf
50μsto2mswhenconnectedtoa
resistiveloadof100Ω
7.1.3.1a.7 Activecurrentdrivecapability,IAout 180mA
7.1.3.1a.8
Freewheelingcurrentcapability(in
Passivestate)
I
AoutduringtP
7.1.3.1a.9 Shortcircuitoutputcurrent,ISC 400mA
7.1.3.1a.10 Faultvoltagetolerance,Vsft 0Vto+20V
7.1.3.1a.11 Faultvoltageemission,Vsfe 0Vto+19V
7.1.3.2 Receiver circuit
a. ThereceivercircuitshallmeetthecharacteristicsspecifiedinTable72.
Table72:LVHPCreceivercharacteristics
ReferenceCharacteristics Value
7.1.3.2.a.1 Circuittype Relayoroptocoupler
7.1.3.2a.2 Transfer DCcoupled
7.1.3.2a.3 Activelevelatunitinputterminal,VAin 11Vto16V
7.1.3.2a.4
Passivecurrentatunitinputterminal(no
activation),I
Pin
200μA
7.1.3.2a.5 Passiveleveltransientimmunity,tPtran
Noactivationforpulsesuptothe
activelevel100μswide
7.1.3.2a.6 Loadcurrent,Iload 180mA(at16V)
7.1.3.2a.7 Inputstochassisisolation,Ziso >1MΩ
7.1.3.2a.8 Faultvoltageemission,Vrfe 0Vto+19V
7.1.3.2a.9 Faultvoltagetolerance,Vrft 0Vto+20V
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7.1.4 High voltage high power command (HV-
HPC) electrical characteristics
7.1.4.1 HV-HPC source circuit
a. The HVHPC source circuit shall meet the characteristics specified in
Table73.
Table73:HVHPCsourcecharacteristics
Reference Characteristic Value
7.1.4.1a.1 Circuittype Singleendeddriverreturnoverwire
7.1.4.1a.2 Transfer DCcoupled
7.1.4.1a.3 Activestateoutputvoltage,VAout 22Vto29V
7.1.4.1a.4 Passivestateoutputleakagecurrent,IPout <100μA
7.1.4.1a.5 Pulsewidth,tP
4msto1024ms(systemdesign
selectabledependingonreceiver
characteristics)
7.1.4.1a.6 Outputvoltageriseandfalltimes,tr,tf
50μsto2mswhenconnectedtoa
resistiveloadof200Ω
7.1.4.1a.7 Activecurrentdrivecapability,IAout 180mA
7.1.4.1a.8
Freewheelingcurrentcapability(in
passivestate)
IAoutduringtP
7.1.4.1a.9 Shortcircuitoutputcurrent,ISC 400mA
7.1.4.1a.10 Faultvoltagetolerance,Vsft 0Vto+33V
7.1.4.1a.11 Faultvoltageemission,Vsfe 0Vto+32V
7.1.4.2 HV-HPC receiver circuit
a. The HVHPC receiver circuit shall meet the characteristics specified in
Table74.
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Table74:HVHPCreceivercharacteristics
Reference Characteristic Value
7.1.4.2a.1 Circuittype Relayoroptocoupler
7.1.4.2a.2 Transfer DCcoupled
7.1.4.2a.3 Activelevelatunitinputterminal,VAin 21Vto29V
7.1.4.2a.4
Passivecurrentatunitinputterminal(no
activation),I
Pin
200μA
7.1.4.2a.5 Passiveleveltransientimmunity,tPtran
Noactivationforpulsesuptotheactive
level100μswide
7.1.4.2a.6 Loadcurrent,Iload 180mA(at29V)
7.1.4.2a.7 Inputstochassisisolation,Ziso >1MΩ
7.1.4.2a.8 Faultvoltageemission,Vrfe 0Vto+32V
7.1.4.2a.9 Faultvoltagetolerance,Vrft 0Vto+33V
7.1.5 High current high power command (HC-
HPC) electrical characteristics
7.1.5.1 HC-HPC source circuit
a. The HCHPC source circuit shall meet the characteristics specified in
Table75.
Table75:HCHPCsourcecharacteristics
ReferenceCharacteristic Value
7.1.5.1a.1 Circuittype Singleendeddriverreturnoverwire
7.1.5.1a.2 Transfer DCcoupled
7.1.5.1a.3 Activestateoutputvoltage,VAout 22Vto29V
7.1.5.1a.4 Passivestateoutputleakagecurrent,IPout <1mA
7.1.5.1a.5 Pulsewidth,tP
4msto1024ms(systemdesign
selectabledependingonreceiver
characteristics)
7.1.5.1a.6 Outputvoltageriseandfalltimes,tr,tf
50μsto2mswhenconnectedtoa
resistiveloadof50Ω
7.1.5.1a.7 Activecurrentdrivecapability,IAout 600mA
7.1.5.1a.8
Freewheelingcurrentcapability(in
passivestate)
IAoutduringtP
7.1.5.1a.9 Shortcircuitoutputcurrent,ISC 1A
7.1.5.1a.10 Faultvoltagetolerance,Vsft 0Vto+33V
7.1.5.1a.11 Faultvoltageemission,Vsfe 0Vto+32V
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7.1.5.2 HC-HPC receiver circuit
a. The HCHPC receiver circuit shall meet the characteristics specified in
Table76.
Table76:HCHPCreceivercharacteristics
ReferenceCharacteristic Value
7.1.5.2a.1 Circuittype Relay
7.1.5.2a.2 Transfer DCcoupled
7.1.5.2a.3 Activelevelatunitinputterminal,VAin 20Vto29V
7.1.5.2a.4
Passivelevelatunitinputterminal(no
activation),I
Pin
2mA
7.1.5.2a.5 Passiveleveltransientimmunity,tPtran
Noactivationforpulsesuptotheactive
level1mswide
7.1.5.2a.6 Loadcurrent,Iload 600mA(at29V)
7.1.5.2a.7 Inputstochassisisolation,Ziso >1MΩ
7.1.5.2a.8 Faultvoltageemission,Vrfe 0Vto+32V
7.1.5.2a.8 Faultvoltagetolerance,Vrft 0Vto+33V
7.1.6 Wiring type
a. Bothtwistedntuplesandtwistedshieldedntupleslinesmaybeused.
b. Shield shall be connected to structure ground on source and receiver
side.
7.1.7 High power command interface arrangement
The interface arrangement is presented in Figure 71, which shows a specific
implementationtakenasanexample,butotherimplementationsconformingto
requirementsarenotexcluded.
V+
Source Receiver
Figure71:HPCinterfacearrangement
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7.2 Low power command (LPC) interface
7.2.1 General
The low power (LPC) command interfaces are intended for driving opto
couplerchannels.
Two types of optocoupler interfaces are considered namely the optocoupler
pulseinterface,LPCP,andtheoptocouplerstaticbilevelinterface,LPCS.
Thelow power commandconsistsof asingle signal, LPC_OUT(H), generated
by
thecoreelement.Thisisconnectedbyasingleendedcircuittotheinputat
the peripheral element. The interface is entirely controlled from the core
element.
7.2.2 Low power command interface
7.2.2.1 Low power command - LPC_OUT(H) signal
a. Thecoreelementshall
1. provideanLPC_OUT(H)signal,and
2. drivesuchasignal.
7.2.2.2 Low power command - LPC_OUT(H) signal passive
state
a. ThepassivestateoftheLPC_OUT(H)signalshallbelow.
7.2.2.3 Low power command - LPC_OUT(H) signal active
state
a. TheactivestateoftheLPC_OUT(H)signalshallbehigh.
7.2.2.4 Low power command output – driver unpowered
a. TheLPC_OUT(H)outputsignalshallbeinpassivestatewhenthedriver
isunpowered.
7.2.2.5 Low power command configuration
a. The low power discrete pulse command source shall be referenced to
sourcesignalground.
b. Theloadshallbeisolatedfromanyuserelectricalreference.
7.2.2.6 Low power command short circuit protection
a. The low power pulse command source shall be short circuit proof for
shortcircuitstosourceorreceiversignalgroundandstructure.
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7.2.3 LPC electrical characteristics
7.2.3.1 Source circuit
a. The source circuit shall meet the characteristics specified in Figure 72
andTable77.
NOTE Figure72showstheLPCsourcehighleveloutput
voltagevs.loadcurrent.Atypicalloadisindicated
asadashedline.
Table77:LPCsourcecharacteristics
ReferenceCharacteristics Value
7.2.3.1a.1 Circuittype Singleendeddriverreturnoverwire
7.2.3.1a.2 Transfer DCcoupled
7.2.3.1a.3 Outputresistance,Rout 370Ωto430Ω
7.2.3.1a.4
Activesignalopencircuitoutputvoltage,
V
Aout
4,4Vto5,5V
7.2.3.1a.5
Passivesignalopencircuitoutputvoltage,
V
Pout
0Vto0,5V
7.2.3.1a.6 Faultvoltageemission,Vsfe 7Vwithasourceimpedance350Ω
7.2.3.1a.7 Faulttolerance Continuousshortcircuit
7.2.3.1a.8
PulsewidthforLPCP
4ms≤td≤120ms
4.4V
5.5V
Vout
Iout
Rout,min =
370 ohm
Rout,max =
430 ohm
10.2mA 14.9mA
Typical load line
Figure72:LPCactivesignaloutputvoltagevs.loadcurrent
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7.2.3.2 Receiver circuit
a. ThereceivercircuitshallmeetthecharacteristicsspecifiedinTable78.
Table78:LPCreceivercharacteristics
ReferenceCharacteristics Value
7.2.3.2a Circuittype Optocoupler,passiveload
7.2.3.2b Transfer DCcoupled
7.2.3.2c Activeinputsignal,VAin
4,4Vto5,5Vthrougha370Ωto450Ω
sourceresistance
7.2.3.2d Passiveinputsignal,VPin 0Vto0,5V
7.2.3.2e Faultvoltagetolerance,Vrft 7Vwithasourceimpedanceof350Ω
7.2.3.2f Inputtochassisisolation,Ziso>1MΩ
7.2.4 Wiring type
a. Bothtwistedntuplesandtwistedshieldedntupleslinesmaybeused.
b. Shield shall be connected to structure ground on source and receiver
side.
7.2.5 Interface arrangement
TheschemedepictedinFigure73isapplicabletobothLPCPandLPCS.The
figure shows a specific implementation taken as an example, but other
implementationscomplianttorequirementsarenotexcluded.
Figure73:LPCPandLPCSinterfacearrangement
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8
Serial digital interfaces
8.1 Foreword
This clause refers to the implementation of 16bit serial digital point to point
interfacesasspecifiedinclause8.2.
Otherserialdigitalpointtopointinterfacesmaybeusedinspaceapplications.
They are not covered by this Standard. However, all digital interfaces
referencing RS422 as the physical layer
(e.g. synchronization pulses) are
recommendedtocomplywiththis specificationforelectricalcharacteristicsas
inclause8.8.
8.2 General principles of serial digital interfaces
8.2.1 Overview
8.2.1.1
The serial digital interfaces are used to exchange digital data words between
core and peripheral elements. The interface timing and clocking signals are
controlledbythecoreelement.
Aserialdigitalinterfacewhichreadsdatafromtheperipheralelementintothe
core element is called an input serial digital (ISD) interface.
A serial digital
interfacewhichwritesdataoutfromthecoreelementtotheperipheralelement
iscalledanoutput serialdigital(OSD)interface. A thirdclassof serial digital
interface is also introduced in this standard, namely the bidirectional serial
digital(BSD)interface.
For space applications, serial digital
interfaces shall be implemented in
balanced differential form. In this form each signal is carried by a pair of
conductorsandthelevelofthesignalisdeterminedbythedifferentialvoltage
betweenthoseconductors.
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8.2.1.2
Theserialdigitalinterfacesarebasedonfivesignals,namely:
GATE_WRITE provided by the core element which indicates when a
writetransfer(fromcoretoperipheral)isunderway,
GATE_READprovidedbythecoreelementwhichindicateswhenaread
transfer(fromperipheraltocore)isunderway,
DATA_CLK_OUTprovided
bythecoreelementwhichcontrolsthedata
transfertiming,
DATA_OUTprovidedbythecoreelementinthecaseofoutputandbi
directionalinterfaces,and
DATA_INprovided bythe peripheralelement inthe caseof inputand
bidirectionalinterfaces.
Inapracticalimplementation,theDATA_CLK_OUTand,
foroutputinterfaces,
the DATA_OUT signal can be distributed to several devices. However, each
devicehasitsownuniqueGATE_WRITE(READ)signal.
SignalsinFigure82andFigure84indicatetheexpectedTRUElinewaveform
ofthedifferentialinterface.DATA_OUTandDATA_INlowdenotesalogic‘0’
andthe
correspondingHIGHdenotesalogic‘1’.
Theserialinterfacetiminginthisstandardisspecifiedinproportiontothebit
period (t
b), which is implementation dependent: once it is specified by the
designer,theothercharacteristicsaredefinedasafunctionoft
b.
Asspecifiedin8.2.2,itisimportantthattheperipheralelementisdesignedto
becompatiblewithanyt
bspecifiedinthisStandard.
Inadditionthestandardprovidessomerecommendedimplementationoptions.
These interfaces correspond to the 16bit digital channel telemetry interfaces
andthe 16bitmemory loadcommands described in TTCB01butwithsome
modifications. Most significantly, none of these word exchanges need be
aligned
withtheOBDHbusinterrogationslotinterval.
NOTE1 This is arelaxation ofrequirements and is inline
withthephilosophyof supporting systemswhich
useMILSTD1553BinsteadoftheESAOBDHbus.
NOTE2 Where an ESA OBDH bus is being used, this
standard does not preclude
synchronisation with
the interrogation slot intervals, but does not
specifyitsuse.
NOTE3 16bittransfersarenowpreferablyperformedina
singleburstratherthanintwo8bit.
8.2.2 General requirements
a. The physical layer of serial digital interfaces shall conform to the
requirementsinANSI/TIA/EIA422andthosespecifiedinthisclause8of
thisStandard.
b. Theperipheralelementshouldbedesignedtobecompatiblewithanyt
b
specifiedin8.3.4.8and8.4.4.9.
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8.3 16-bit input serial digital (ISD) interface
8.3.1 16-bit input serial digital interface
description
Thesignalarrangementforthe 16bitinputserialdigital interfaceisshownin
Figure82.
The 16bit input serial digital interface consists of three signals, namely
GATE_READ, DATA_CLK_OUT, and DATA_IN. The GATE_READ and
DATA_CLK_OUT are used to control the operation of the interface and are
drivenbythe
coreelement.TheDATA_INsignalisusedtocarrythedatatobe
transferredandisdrivenbytheperipheralelement.
GATE_READ
DATA_CLK_OUT
DATA_IN
CORE
PERIPHERAL
Figure81:16bitinputserialdigital(ISD)interfacesignalarrangement
8.3.2 Signals skew
8.3.2.1 Introduction
In the values listed in Table 81 a skew is considered between any pair of
signals or subsequent edges of the same signal to account for components
characteristicsand/orharnessroutingasymmetry.
8.3.2.2 Provisions
a. MaximumskewmeasuredatcoresideshallbeΔt=0,02×tb.
b. MaximumskewmeasuredatperipheralsideshallbeΔt=0,04×t
b.
8.3.3 ISD interface timing specification
ThetimingdiagramshowninFigure82andthetimingparametersinTable81
specifythe signaltiming oftheoperationalrequirementsspecifiedin8.3.4for
the16bitinputserialdigitalinterface.
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A data transfer is initiated by the core element asserting GATE_READ. In
responsetothistheperipheralelementplacesthevalueofthemostsignificant
bit(bit0)ofthedatawordontheDATA_INline.
AftertheGATE_READfallingedge(t
cd),thecoreelementgeneratesasequence
of sixteen low going pulses out onto the DATA_CLK_OUT line. The core
element samples the DATA_IN line on the falling edge of each
DATA_CLK_OUTpulse.Thissamefallingedgecausestheperipheralelement
tooutputthenextbitofthedatawordonthe
DATA_INline.
TheDATA_INlinestateisnotsampledafterthelastDATA_CLK_OUTfalling
edgeandcanreturntoitsquiescentʹdonʹtcareʹstate.
Sometime after the last DATA_CLK_OUT falling edge the core element de
assertstheGATE_READsignalindicatingtheendofthedatatransfer(t
gd).
GATE_READ
UP can occur at the same time, or even slightly before, the last
DATA_CLK_OUT
UP.TheGATE_READsignalissubsequentlykeptdeasserted
forashortperiod(t
rec)toenabletheperipheralelementtorecoverreadyforthe
nextdatatransfer.
GATE_READ
DATA_CLK_OUT
DATA_IN
10 2 3 4 5 6 7 8 9 10 11 12 13 14 15
t
rec
t
s
t
b0
t
cd
t
ch
t
gd
t
dh
t
b
t
dv
18916
t
b8
Figure82:16bitinputserialdigital(ISD)interface
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Table81:16bitinputserialdigital(ISD)interfacecharacteristics
Reference Parameter Description Maximum Minimum
8.3.3a.1 tb Bitsamplinginterval tb(MAX) tb(MIN)
8.3.3a.2 ts Repeatedtransferperiod
a
tb×17
8.3.3a.3.(a)
GATE_READ
DOWNtobit0datavalid,
measuredatperipheralelement
t
b×0,2‐
8.3.3a.3.(b)
t
b0
GATE_READ
DOWNtobit0datavalid,
measuredatcoreelement
t
b×0,3‐
8.3.3a.4 tcd
Clockdelay,GATE_READ
DOWNtofirst
DATA_CLK_OUT
DOWN
t
b×7+Δt tb/2Δt
8.3.3a.5 tdh DataholdafterDATA_CLK_OUTDOWN ‐ 0
8.3.3a.6.(a)
NextdatavalidafterDATA_CLK_OUT
DOWN,
measuredatperipheralelement
t
b×0,7‐
8.3.3a.6.(b)
t
dv
NextdatavalidafterDATA_CLK_OUT
DOWN,
measuredatcoreelement
t
b×0,8‐
8.3.3a.7.(a)
TimeDATA_CLK_OUThigh(clockduty
cycle)measuredatcoreelement
tb/2×1,1 tb/2×0,9
8.3.3a.7.(b)
t
ch
TimeDATA_CLK_OUThigh(clockduty
cycle)measuredatperipheralelement
t
b/2×1,2 tb/2×0,8
8.3.3a.8 tgd
Gatingdelay,lastDATA_CLK_OUT
DOWNto
GATE_READ
UP
t
b×4+Δt tb/2Δt
8.3.3a.9 trec
Recoveryinterval,GATE_READ
UPto
GATE_READ
DOWN
t
bΔt
8.3.3a.10 tb8 Extensionofgap
b
betweenclockpulse8and9 tb×8 0
a
Thetransferperiodiscalculatedasfollows:ts=tcd+tgd+trec+15·tb
b
Thisistoallow8bitburstsinTTCB01fashion
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8.3.4 16-bit input serial digital interface: signal
description
8.3.4.1 16-bit input serial digital - signals
a. The 16bit input serial digital interface shall consist of three signals
namedGATE_READ,DATA_CLK_OUT,andDATA_IN.
NOTE1 GATE_READ and DATA_CLK_OUT are active
lowsignals.
NOTE2 Signalsaredifferentialsignals.
8.3.4.2 16-bit input serial digital - GATE_READ signal
quiescent state
a. During quiescence, i.e. when no data transfer is taking place, the
GATE_READsignalshallbemaintainedatahighlogiclevelbythecore
element.
8.3.4.3 16-bit input serial digital - DATA_CLK_OUT signal
a. The DATA_CLK_OUT signal shall comprise sixteen low going pulses
duringeachdatatransferoperation.
b. The DATA_CLK_OUT burst shall last 16 times the bit sampling
pseudoperiod (tb) plusthe optionalextensionof theclockgapbetween
clockpulse8and9(tb8).
8.3.4.4 16-bit input serial digital - DATA_CLK_OUT signal
quiescent state
a. Peripheralelements shallignore theDATA_CLK_OUT signal when the
GATE_READsignalisnotasserted.
NOTE Thereasonisthatduringquiescence,i.e.whenno
datatransferistakingplace,theDATA_CLK_OUT
signal can oscillate (e.g. if it is shared with other
peripheralelements).
8.3.4.5 16-bit input serial digital - DATA_IN signal
a. TheperipheralelementshallprovideaDATA_INsignal.
b. Theperipheralelementshallensurethat thedataon thissignalis valid
andstableoneveryDATA_CLK_OUTfallingedgewhenGATE_READis
asserted.
8.3.4.6 16-bit input serial digital - DATA_IN signal
quiescent state
a. Duringquiescence,thecoreelementshalldisregardtheDATA_INsignal.
b. PeripheralelementshouldmaintaintheDATA_INsignalinastablestate.
NOTE Theactuallevelusedbytheperipheralelementis
notmandated.
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8.3.4.7 16-bit input serial digital - data transfer
a. Data transfer on the 16bit ISD shall be started by the core element,
assertingtheGATE_READsignal.
b. InresponsetotheGATE_READ
DOWN theperipheralelementshallsetthe
DATA_INsignaltothevalueofthemostsignificantbit,bit0,ofthedata
word.
c. ThecoreelementshallthensampletheDATA_INsignaloneachfalling
edgeoftheDATA_CLK_OUT(DATA_CLK_OUT
DOWN).
d. After each DATA_CLK_OUT fallingedge (DATA_CLK_OUT
DOWN ), the
peripheralelementshallsetthevalueoftheDATA_INsignaltothevalue
ofthenextmostsignificantbit.
NOTE ThatmeansthatifthecurrentvalueofDATA_IN
isbitn,thenewvalueofDATA_INisbitn+1.
e. Whenthe8thclockpulseonDATA_CLK_OUT
hasbeengenerated,the
gaptothenextclockpulsemaybeincreasedbyuptot
b×8.
f. Whenbit15ofDATA_INisreached,DATA_INmaybesettoanyvalue;
NOTE The reason is that the next value of DATA_IN is
not important since the DATA_IN signal is not
sampledafterthis.
8.3.4.8 16-bit input serial digital - bit sampling interval, t
b
a. The bit sampling interval, tb, i.e. the interval between successive
DATA_CLK_OUT rising edges, should be selected from the options
showninTable82.
Table82:tbvalues
Reference tb(MIN) tb(MAX)
Maximum
sustainabledata
t (Kb )
8.3.4.8a 7,95μs 8,05μs 118,387
8.3.4.8b 7,59μs 7,67μs 124,002
8.3.4.8c 3,95μs 4,05μs 238,273
8.3.4.8d 3,78μs 3,85μs 248,988
8.3.4.9 16-bit input serial digital - sampling period, t
s
a. The sampling period, ts, defined as the minimum period between one
GATE_READ
DOWN and the next opportunity for a GATE_READDOWN,
shallbenotlessthant
b×17.
NOTE Thetransferperiodiscalculatedasfollows:
t
s=tcd+tgd+trec+15tb.
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8.3.4.10 16-bit input serial digital - data hold after
DATA_CLK_OUT
UP
, t
dh
a. ThedataholdtimeaftertheDATA_CLK_OUTfallingedge,tdh,shallbe
notlessthan0.
NOTE This ensures that the propagation delay always
givesenoughmargintoholdthedata.
8.4 16-bit output serial digital (OSD) interface description
8.4.1 16-bit output serial digital interface
description
Thesignalarrangementforthe16bitoutputserialdigitalinterfaceisshownin
Figure 82. Unless otherwise specified, signal properties are measured at the
coreinterface.
The 16bit output serial digital interface consists of three signals, namely
GATE_WRITE,DATA_CLK_OUT,andDATA_OUT.Allofthreethesesignals
aredriven
bythecoreelement.The GATE_WRITEand DATA_CLK_OUTare
usedtocontroltheoperationoftheinterfaceandtheDATA_OUTsignalisused
tocarrythedatatobetransferred.
GATE_WRITE
DATA_CLK_OUT
DATA_OUT
CORE
PERIPHERAL
Figure83:16bitoutputserialdigital(OSD)interfacesignalarrangement
8.4.2 Signals skew
8.4.2.1 Overview
In the values listed in Table 83 a skew is considered between any pair of
signals or subsequent edges of the same signal to account for component
characteristicsand/orharnessroutingasymmetry.
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8.4.2.2 Provisions
a. MaximumskewmeasuredatcoresideshallbeΔt=0,02×tb.
b. MaximumskewmeasuredatperipheralsideshallbeΔt=0,04×t
b.
8.4.3 OSD interface timing specification
ThetimingdiagramshowninFigure84andthetimingparametersinTable83
specifythetimingoftheoperationalrequirementsspecifiedin8.4.4forthe16
bitoutputserialdigitalinterface.
Adatatra nsferisstartedbythecoreelementassertingtheGATE_WRITEsignal
to indicate that a
data transfer is underway. After this (tb0) the core element
placesthevalueofthemostsignificantdatabit(bit0)ontheDATA_OUTline.
SometimeaftertheGATE_WRITE
DOWN,16lowgoingpulsesareoutputonthe
DATA_CLK_OUT signal. Each bit of the data word, including bit0 is
guaranteedvalidontheDATA_CLK_OUTfallingedgeandforagivenperiod
before,datasetuptimet
su,andafterit,dataholdtimetdh.
GATE_WRITE is deasserted after the last GATE_CLK_OUT
DOWN. This de
assertion can thus occur before the final GATE_CLK_OUT
UP. GATE_WRITE
thenisnotreassertedbeforetheinterfacerecoveryperiodhasexpired.
GATE_WRITE
DATA_CLK_OUT
DATA_OUT
10 2 3 4 5 6 7 8 9 10 11 12 13 14 15
t
rec
t
s
t
b0
t
cd
t
ch
t
gd
t
dh
t
b
t
dv
t
b8
18916
Figure84:16bitoutputserialdigital(OSD)interface
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Table83:16bitoutputserialdigital(OSD)interfacecharacteristics
Reference Parameter Description Maximum Minimum
8.4.1a.1 tb Bitsamplinginterval tb(MAX) tb(MIN)
8.4.1a.2 ts Repeatedtransferperiod
a
t
b
×17
8.4.1a.3 tb0 Bit0datavalidafterGATE_WRITEDOWN tb/4‐
8.4.1a.4 tcd
Clockdelay,GATE_WRITE
DOWNtofirst
DATA_CLK_OUT
DOWN
t
b×7+Δt tb/2Δt
8.4.1a.5 tdh DataholdafterDATA_CLK_OUTDOWN‐ tb/8Δt
8.4.1a.6 tsu DatavalidbeforeDATA_CLK_OUTDOWN‐ tb/4Δt
8.4.1a.7.(a)
TimeDATA_CLK_OUThigh(clockdutycycle)
measuredatcoreelement
tb/2×1,1 tb/2×0,9
8.4.1a.7.(b)
t
ch
TimeDATA_CLK_OUThigh(clockdutycycle)
measuredatperipheralelement
t
b/2×1,2 tb/2×0,8
8.4.1a.8 tgd
Gatingdelay,lastDATA_CLK_OUT
DOWNto
GATE_WRITE
UP
t
b
×4+Δt t
b
/2Δt
8.4.1a.9 trec
Recoveryinterval,GATE_WRITE
UPto
GATE_WRITE
DOWN
t
b
Δt
8.4.1a.10 tb8 Extensionofgap
b
betweenclockpulse8and9 tb×8 0
a
 Thetransferperiodiscalculatedasfollows:ts=tcd+tgd+trec+15·tb
b
 Thisistoallow8bitburstsinTTCB01fashion
8.4.4 16-bit output serial digital interface signal
description
8.4.4.1 16-bit output serial digital - signals
a. The 16bit output serial digital interface shall consist of three signals
namedGATE_WRITE,DATA_CLK_OUT,andDATA_OUT.
b. Signalsshallbedifferential.
8.4.4.2 16-bit output serial digital - GATE_WRITE signal
a. The core element shall provide a GATE_WRITE signal asserted by the
coreelementduringadatatransferoperation.
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8.4.4.3 16-bit output serial digital - GATE_WRITE signal
quiescent state
a. During quiescence, i.e. when no data transfer is taking place, the
GATE_WRITEsignalshallbemaintainedatahighlogiclevelbythecore
element.
8.4.4.4 16-bit output serial digital - DATA_CLK_OUT signal
a. ThecoreelementshallprovideaDATA_CLK_OUTsignal.
b. The DATA_CLK_OUT signal shall comprise sixteen low going pulses
duringeachdatatransferoperation.
c. The DATA_CLK_OUT burst shall last 16 times the bit sampling
pseudoperiod (t
b) plus the optional extension of the clock gap between
clockpulses8and9(t
b8).
8.4.4.5 16-bit output serial digital - DATA_CLK_OUT signal
quiescent state
a. Peripheralelements shallignore theDATA_CLK_OUT signal when the
GATE_WRITEsignalisnotasserted.
NOTE Thereasonisthatduringquiescence,i.e.whenno
datatransferistakingplace,theDATA_CLK_OUT
signal can oscillate (e.g. if it is shared with other
peripheralelements).
8.4.4.6 16-bit output serial digital - DATA_OUT signal
a. Thecoreelementshall providea DATA_OUTsignalusedtotransferthe
datawordbitserially.
8.4.4.7 16-bit output serial digital - DATA_OUT signal
quiescent state
a. Peripheral elements shall ignore the DATA_OUT signal when the
GATE_WRITEsignalisnotasserted.
NOTE Thereasonisthatduringquiescence,i.e.whenno
data transfer is taking place, the DATA_OUT
signal can change (e.g. if it is shared with other
peripheralelements).
8.4.4.8 16-bit output serial digital - data transfer
a. Data transfer on the 16bit OSD shall be started by the core element,
assertingtheGATE_WRITEsignal.
b. Shortly after the GATE_WRITE
DOWN the core element shall set the
DATA_OUTsignal to the value ofthe mostsignificant bit, bit 0, of the
datawordtobetransferred.
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c. The core element shall ensure that the DATA_OUT signal is valid on
eachfallingedgeoftheDATA_CLK_OUT(DATA_CLK_OUT
DOWN)when
GATE_WRITEisasserted.
d. The DATA_OUT signal shall meet the data setup and hold times as
specifiedinTable83.
e. Shortly after (after t
dh) each DATA_CLK_OUT falling edge
(DATA_CLK_OUT
DOWN),the core element shallupdate the valueof the
DATA_OUTsignaltothevalueofthenextmostsignificantbit.
NOTE That means that if the current value of
DATA_OUTisbitn,thenewvalueofDATA_OUT
isbitn+1.
f. When the 8
th
clock pulse on DATA_CLK_OUThas been generated, the
gaptothenextclockpulsemaybeincreasedbyuptot
b×8.
g. Whenbit15ofDATA_INisreached,anyvaluemaybeused;
NOTE ThereasonisthatthenextvalueofDATA_OUTis
not important since the peripheral element does
notsampletheDATA_OUTsignalafterthis.
8.4.4.9 16-bit output serial digital - bit sampling interval, t
b
a. The bit sampling interval, tb, i.e. the interval between successive
DATA_CLK_OUT rising edges, should be selected from the options
showninTable82.
8.4.4.10 16-bit output serial digital - sampling period, t
s
a. The sampling period, ts, defined as the minimum period between one
GATE_WRITE
DOWN and the next opportunity for a GATE_WRITEDOWN,
shallbenotlessthant
b×17.
NOTE Thetransferperiodiscalculatedasfollows:
t
s=tcd+tgd+trec+15tb.
8.5 16-bit bi-directional serial digital (BSD) interface
description
The 16bit bidirectional serial digitalinterface providesa bidirectional serial
digitaldatatransfercapabilityusingfivesignalsasshowninFigure85:
GATE_WRITE,
GATE_READ,
DATA_CLK_OUT,
DATA_OUT,and
DATA_IN.
TheGATE_WRITEandGATE_READsignalsareusedtoindicatethedirection
ofthetransfer.
Thesignaltimingduringoutputtransfersisidenticaltothatfor
the16bitoutputserialdigitalinterfaceandduringinputtransfersitisidentical
tothe16bitinputserialdigitalinterface.
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GATE_WRITE
GATE_READ
DATA_IN
CORE
PERIPHERAL
DATA_CLK_OUT
DATA_OUT
(OSD)
(OSD)
(ISD)
(ISD)
(OSD + ISD)
Figure85:16bitbidirectionalserialdigitalinterfacesignalarrangement
Therearetwoadvantagesofferedbythisinterface.
Firstly,itoffersthepossibilityofwritingadatavalueouttoaperipheral
elementandthenreadingthesamevaluebackinordertoverifythatthe
writeoperationwasperformedcorrectly.
Secondly, the interface can be expanded to address
more than one
registerlocationwithinaperipheralelementusingonlytwoextrasignals
for each additional register. The extra signals used are a dedicated
GATE_WRITE(READ)signalforeachnewregistertobeaccessed.Allof
the other signals can be common to all registers. This means that n
registers
can be accessed using only 2n + 3 signals which can lead to
significantsavingsintermsofcablesandconnectors.
During an input transf er the data is input via the DATA_IN signal and the
DATA_OUTsignalassumesitsquiescencestate.Duringadataoutputtransfer
thedataisoutputon
theDATA_OUTsignalandtheDATA_INsignalassumes
itsquiescencestate.
8.6 Serial digital interface electrical circuits description
Theserialdigital interfacecircuitsaretheconductingpaths whichconvey the
data and control signals which make up the interface between the core and
peripheralelements.Eachcircuitconsistsoftheconductorsandanyconnectors
orothercomponentswhichcomprisetheelectricalpath.
Twocircuitsareusedforeachsignal.
Thesecircuitsoperateinabalancedmode
withreferencetothecoreelementdifferentialground potential,i.e.whenone
circuit carries a positive voltage, the complementarycircuit carries a negative
voltageofthesamemagnitude.
Figure 86 shows the relationship between circuits, signals, and the interface
definitionpointfor
balanceddifferentialserialdigitalinterfaces.
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V
OH
V
OL
I
OL
I
OH
I
IL
I
IH
Local
Connection
Points
Point of
Interface
Definition
Core
Element
Peripheral
Element
*
Reference potential for balanced voltage measurements
Output
Circuits
Output
Signal
Input
Signal
Input
Circuits
*
V
IH
V
IL
+ve
-ve
+ve
-ve
I
IL
I
IH
I
OL
I
OH
*
Figure86:Balanceddifferentialcircuitsforserialdigitalinterfaces
8.7 Balanced differential serial digital interface signals
8.7.1 Balanced differential serial digital interface -
GATE_WRITE circuits
a. A balanced differential pair of circuits called GATE_WRITE+ and
GATE_WRITE‐shallbeprovided.
b. Thebalanceddifferentialpairspecifiedin8.7.1ashall
1. bedrivenbythecoreelement,and
2. carrytheGATE_WRITEsignal.
8.7.2 Balanced differential serial digital interface -
DATA_CLK_OUT circuits
a. A balanced differential pair of circuits called DATA_CLK_OUT+ and
DATA_CLK_OUT‐shallbeprovided.
b. Thebalanceddifferentialpairspecifiedin8.7.2a.shall
1. bedrivenbythecoreelement,and
2. carrytheDATA_CLK_OUTsignal.
8.7.3 Balanced differential serial digital interface -
DATA_OUT circuits
a. Foroutputserialdigitalinterfaces,abalanceddifferentialpairofcircuits
calledDATA_OUT+andDATA_OUT‐shallbeprovided.
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b. Thebalanceddifferentialpairspecifiedin8.7.3ashall
1. bedrivenbytheperipheralelement,and
2. carrytheDATA_OUTsignal.
8.7.4 Balanced differential serial digital interface -
DATA_IN circuits
a. Forinputserial digital interfaces,abalanced differentialpair of circuits
calledDATA_IN+andDATA_IN‐shallbeprovided.
b. Thebalanceddifferentialpairspecifiedin8.7.4ashall
1. bedrivenbytheperipheralelement,and
2. carrytheDATA_INsignal.
8.7.5 Balanced differential serial digital interface -
GATE_READ circuits
a. Forbidirectional serial digitalinterfaces,a balanceddifferentialpair of
circuitscalledGATE_READ+andGATE_READ‐shallbeprovided.
b. Thebalanceddifferentialpairspecifiedin8.7.5ashall
1. bedrivenbythecoreelement,and
2. carrytheGATE_READsignal.
8.8 Serial digital interface circuit electrical characteristics
8.8.1 Introduction
ANSI/TIA/EIA422 (hereafter briefly RS422) defines a balanced (differential)
interface;specifyingasingle,unidirectionaldriverwithmultiplereceivers(up
to 32). RS422 will support PointtoPoint, MultiDrop circuits, but not Multi
Point.
AlthoughtheEIAstandarddoesnotshowcircuitgroundingineitheroftheRS
422
circuits,thisStandardincludesrecommendationongroundingin8.8.2a.
8.8.2 Provisions
a. Serialdigitalinterfacecircuitsshouldbegroundedasfollows:
1. The drivers and receivers should be connected directly to circuit
ground.
2. Thecircuitgroundshouldbeconnectedtochassisground.
NOTE1 CablingisnotspecifiedinRS422butinformation
canbefoundin[V11].
NOTE2 Figure
87illustratesthisprovision.
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b. Serial digital interface circuit electrical characteristics shall meet the
requirementsspecifiedinTable84.
NOTE1 Table84includescharacteristicsforcompatibility
with RS422 (indicated with the number (422) in
thetable),andspecificcharacteristics
NOTE2 The values specified herein grant correct
operationsinthe
followingconditions:
maximumsignalfrequency:1MHz;
maximumcablelength:16m;
cable type: Twisted Shielded Pair 120Ω
Impedance.
NOTE3 Compliance to the parameters indicated by the
note (422) in Table 84 can be achieved by use of
thefollowingcircuits:
HS26C(T)31RH
HS26C(T)32RH
HS26CLV31RH
HS26CLV32RH
Items1and2are5Vsupplieddevices,items3and
4 are 3,3 V supplied devices. These devices can
interoperate and comply with the specification in
Table84.
c. Serial digital interface shall be compliant to the interface arrangement
specifiedinFigure87.

d. Compliance to microcircuits characteristics others than the parameters
indicatedbythenote(422)inTable84.,shallbeverifiedontheprojectby
ReviewofDesignorTest.
Figure87:Exampleofserialdigitalinterfacearrangement
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Table84:Serialdigitalinterfaceelectricalcharacteristics
Reference Characteristics Value Type Notes
SOURCECIRCUIT
8.8a.1 Electricalcharacteristics Differential (422)
8.8a.2
Differentialoutput
voltageopencircuit,V
OC
1,8V≤|V
OC|≤6,0V Specific
8.8a.3
OutputvoltageTRUEand
COMPlines,V
e
V
e≤6V (422)
8.8a.4
Differentialoutput
impedance,Z
out
105Ω≤Z
out≤135Ω Specific Note1
8.8a.5
Shortcircuitoutput
current,I
A
|I
A|≤150mAforeachterminal
toground
(422)
8.8a.6 Risetime,tr
t
r≤0,1×tb iftb≥200ns
t
r≤20nsiftb≤200ns
(422) Note2
8.8a.7
Outputleakagecurrentin
poweroff,I
O
|I
O|≤100μA (422) Note3
8.8a.8
Faultvoltageemission,
V
sfe
0Vto7V(through50Ωminimumseries
resistance)
Specific
8.8a.9
Faultvoltagetolerance,
V
sft
1,5Vto7V(appliedthrough1kΩseries
resistanceRis)
Specific
RECEIVERCIRCUIT
8.8a.10 Electricalcharacteristics Differential (422)
8.8a.11 Seriesprotection,Ris 2*1kΩ Specific
8.8a.12
Maxinputvoltage(each
inputw.r.t.ground),V
I
±10V (422) Note4
8.8a.13
Commonmode
acceptance(V1+V2)/2,V
CM
4Vto+7V Specific Note5
8.8a.14
Differentialinputvoltage,
V
DI
±|600mVto6V|
eachvoltageinthisrangemustbe
interpretedasvalidsignal
Specific Note6
8.8a.15
Faultvoltageemission,
V
rfe
0Vto5,5V(through1kΩseriesresistanceR
is) Specific
8.8a.16
Faultvoltagetolerance,
V
rft
1,5Vto8,5V Specific
Note1: Outputimpedancetobematchedwith120Ωcableimpedance.RecommendedrangeoftheRosresistors
between50Ωand60Ω,considering10Ωtypicaldriveroutputimpedance,whenusingHS
26C(T)31RH.
Note2: tbtimedurationoftheunitintervalattheapplicabledatarate(normally0,5*periodduration).
Note3: –0,25Vto+6Vappliedattheoutputterminals.
Note4: RS422standardparametersgivenforreferenceonly.
Note5: Thisfigureiscompatiblewithbothperformancesof5V
and3,3Vdevices(HS26CLV32RH).
Note6: Minimumthresholdconsidering1kΩseriesresistors(thedevicescommonlyusedhaveathresholdof
±400mV,forreferenceseeFigure88).
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Figure88:ThresholdlevelsforECSSE5014differentialcircuits
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Annex A (informative)
Tailoring guidelines
Tailoring for this Standard is limited to the adoption of specific discrete
interfaceslistedhereby:
Analoguesignalinterfaces
Analoguesignalmonitor(ASM)interface
Temperaturesensorsmonitor(TSM)interfaces
Bileveldiscreteinputinterfaces
Bileveldiscretemonitor(BDM)interface
Bilevelswitchmonitor(BSM)interface
Pulsedcommandinterfaces
Highpowercommand(HPC)interfaces
Lowpowercommand(LPC)interface
Serialdigitalinterfaces
16bitinputserialdigital(ISD)interface
16bitoutputserialdigital(OSD)interfacedescription
16bitbidirectionalserialdigital(BSD)interfacedescription
Modificationofexistingoradditionofrequirementswithinaspecificinterface
definitionshouldnotbedone.
ECSSEST5014C
31July2008
70
Bibliography
ECSSSST00 ECSSsystem‐Description,implementationand
generalrequirements